FPGA claims 10K usable gates
The CP21200, the second in Crosspoint's CP20K family, is said to allow
system clocks of 40 to 50 MHz. Its fine-grained channeled gate-array
structure and workstation-based design tools make it familiar to ASIC
designers at once; 196 I/O pins can be input, output, or bidirectional.
Three other pins can be used for JTAG or as Schmitt-trigger inputs. Four
clock pins can also alternatively be Schmitt triggers. Four independent
low-skew clock networks are provided. Packages are 299-pin PGA or 208-pin
QFP. ($1,100 ea/100–samples now.) Crosspoint Solutions, Inc. Santa
Clara, CA Ann Berry 408-988-1584 Fax 408-980-9594
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