FPGA design suite aids FP math operations

ISE Design Suite 13.3 features new capabilities for DSP designers to easily implement bit-accurate single, double and full custom precision floating-point math operations in Xilinx FPGAs. This flow is available through System Generator for DSP.

With version 13.3, the Floating-Point Operator core allows a range of floating-point arithmetic operations, without the need for VHDL or Verilog coding. It also adds Red Hat Enterprise Linux 6 and provides productivity enhancements for Logic, Embedded and System Edition users. All editions contain enhancements to Plug-and-Play IP and device support for 7 series devices. (From $2,995; DSP Edition, $3,895 — available now.)

By Jim Harrison

Xilinx , San Jose , CA
Sales 408-559-7778
www.xilinx.com