The ISE Design Suite version 12 FPGA development software package has added intelligent clock-gating technology that reduces dynamic power consumption by as much as 30%. The suite also provides advances in timing-driven design preservation, AMBA 4 AXI4-complaint IP support, and an intuitive design flow with partial reconfiguration capabilities.
Partial reconfiguration technology allows the modification of an operating FPGA design by downloading partial bit files without interrupting the operation of the remaining logic. It can allow in-field updates to a system while it is operating. The open ABMA 4 AXI4 interconnect protocol, developed by ARM, eases integration of IP from Xilinx and third-party providers. The package also provides an average of two times faster logic synthesis. (From $2,995 — available now.)
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