FPGA design suite has advanced place & route

FPGA design suite has advanced place & route

Version 7.2 of the ispLEVER FPGA design tool suite for features advanced place-and-route algorithms that deliver higher-performance results in as much as 30% less time. The software now supports clock-boosting flow, on some Lattice FPGA families, that can yield up to a 5% increase in FMax with no additional user input.

The tools new place and route techniques can analyze a design and automatically choose the most appropriate algorithm for the topology yielding better results in less time. ($1,295 — available now.)

Lattice Semiconductor , Hillsboro , OR
Sales 503-268-8000

http://www.latticesemi.com