FPGA design suite tackles bottlenecks

The Vivado Design Suite design environment was built from the ground up to accelerate design productivity for the next decade of FPGAs. To address implementation bottlenecks, the package includes a hierarchical device editor and floor planner, a 3 to 15X faster logic synthesis tool with support for SystemVerilog, and a 4X faster, more deterministic, place and route engine that uses analytics to optimize timing, wire length, and routing congestion.

The packages tools have a new shared scalable data model. They provide electronic system-level (ESL) design tools for synthesizing and verifying C-based algorithmic IP; standards-based packaging of both algorithmic and RTL IP for reuse; standards-based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance. The software come in Web, Design, and System versions. Beta version available now, version 1.0 in mid-summer, and added functions through December. (Web version free available now.)

By Jim Harrison

Xilinx , San Jose , CA
Sales 408-559-7778
www.xilinx.com