FPGA reference design links high-speed A/D

The LatticeECP2/M and TI ADS6000 interface reference design supports the Texas Instruments ADS6000 family of A/D converters. The high-speed glueless interface can acquire 14-bit A/D data at rates up to 120 Msamples/s from the chips’ two to four serial channels.

The design uses about 5% of the FPGA’s logic to transfer the A/D codes on the serial source synchronous bus to its embedded block RAM. To facilitate design verification, the design uses a hardware interface card, a TI ADS6425EVM evaluation board, and an advanced evaluation board. (Interface card, LFE2-H-IC-EV, $195, A/D evaluation module, ADS6425EVM, $299—available now.)

Lattice Semiconductor , Hillsboro , OR
Brian Kiernan 503-268-8739

http://www.latticesemi.com