FPGA reference design
runs 143-MHz ZBT
A Virtex FPGA reference design generates an interface between the chip
and synchronous ZBT SRAMs. The synthesizable Verilog design is for 64-K
x 36 pipelined and flow-through devices, but can be adapted to others.
Other available designs interface to SDRAMs. (Free from the Web site.)
Xilinx
San Jose, CA
Amy Hills 408-879-6835
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