FPGAs share chip space with
diffused logic and µP

Motorola Semiconductor (Phoenix, AZ) has announced plans for Core+, an IC product family that will combine FPGA regions along with widely used cores from the company's IP libraries. For products that need all or most of the fixed components on a chip, densities will far exceed anything that could be done entirely in programmable logic. The first device to go into production, the MPACF250, will naturally target the widest possible market in embedded systems.

The initial device will incorporate a Version 2 ColdFire core, compatible with the 68000 instruction set. Other diffused cells will include a dual-port SRAM, cache RAM, two DMA channels, a dual UART, timers, I² C bus, and an 8-bit programmable I/O port. All of these cells will access a three-level internal bus hierarchy that will connect them to SRAM-based FPGA cells and the on-chip RAM.

Like all recent Motorola microprocessor parts, the parts in the Core+ family will include a background debug module that allows development with inexpensive emulator hardware. Existing 68000-based board designs may be reused as single-chip designs on the new device, without incurring NRE charges.

The company expects third-party tools to be available for schematic capture, simulation, and logic synthesis, along with the company's own Programmable Array Design System for the FPGA portion. ColdFire is already supported by compilers, debuggers, and in-circuit emulators. The MPACF250 is slated for availability in the third quarter. For more information, call Connie Schultejans of Motorola Semiconductor at 602-732-2852, fax 602-732-5020, e-mail rpae50@email.sps.mot.com .