Free design kit
for ATM designers
The ATM Design Kit provides Asynchronous Transfer Mode designers with technical
information for designing equipment with the company's FLEX 8000 PLDs. It
includes details on the implementation of a high-speed 16-bit parallel cyclic
redundancy checker as well as an exploration of the issue of traffic control.
The kit provides a sample ATM packet scheduler design, based on a weighted
round-robin scheduling algorithm that schedules input from multiple ports to
one output port. The ATM packet scheduler is designed to support up to 32 ATM
virtual channel groups with a dedicated buffer of up to 1,024 cells per group.
This macrofunction can be modified to meet individual design requirements.
(Free–available now.)
Altera Corp.
San Jose, CA
Literature Dept. 408-894-7144
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