The ADIsimPLL version 3.3 of the PLL circuit design and evaluation tool assists users in evaluating, designing, and troubleshooting RF systems. The tool adds 16 new devices, increases phase noise modeling accuracy and fractional-N spur level estimation, and offers enhancements to the tool’s New Design Wizard, Time Simulation Engine, and Time Domain Simulator features.
To support the new devices, the ADIsimPLL design tool incorporates the ability to derive additional frequency outputs by dividing the VCO signal. The phase noise simulation algorithms have been improved by the addition of the 1/f phase noise contribution from the digital dividers and the phase detector, resulting in highly accurate phase noise predictions from close to the carrier all the way to the broadband noise floor. To assist in estimating the level of fractional-N spurs, a new estimate of the worst-case magnitude of the first three fractional-N spurs is now calculated and displayed on the phase noise plots. (Free — available now.)
Analog Devices , Wilmington , MA
Customer Service 800-262-5643
http://www.analog.com
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