HL5.DEC–IIT–rm
Graphics accelerator chips perform four-operand BitBLT
The architecture, based on IBM's old XGA, claims advantages over 8514A,
even if XGA never becomes a standard
A pair of accelerator chips for PC graphics, one for the ISA bus (the
AGX-14), the other for the VESA local bus (the AGX-15), claim to double
the performance available from other such chips. The performance comes
from the XGA architecture, launched by IBM some time ago. Vivie Lee,
product manager at IIT, the chip vendor, says the architecture was fine,
but IBM's implementation was slow. The speed advantage of the new chips
in real windowing applications comes from the ability to use four operands
for a pixel operation, rather than the source-operator-destination
sequence of the 8514. Thus a source image can be combined with a mask and
a shading pattern all at once to a single destination. A simple
line-drawing function can be combined with a reference pattern to scale
dimensions and angles, useful in 3-D rotation. Demonstrations of these and
other features were shown at Comdex last month on boards by Hercules and
VidTech, among others. A complete ISA subsystem uses nine chips in
addition to memory with the IIT AGX-014. A VESA board needs only six
chips, since it eliminates TTL buffers required by the ISA. If frame
buffers are larger than 2 Mbytes of video RAM, buffering is required for
that. (AGX-014 for ISA, $37 ea/1,000; AGX-015 for VESA local bus, $46
ea/1,000–available now.) Integrated Information Technology, Inc., Santa
Clara, CA Vivie Lee 408-727-1885 Fax 408-980-0432
CAPTION:
These accelerator chips from Integrated Information Technology speed
pixel operations beyond current GUI accelerators.
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