Handheld appliances benefit from low-power CPLDs

Handheld appliances benefit from low-power CPLDs

Flexible programmable logic can be even more attractive to power conscious designers

BY KERRY HOWELL
Lattice Semiconductor
Hillsboro, OR
http://www.latticesemi.com

Designers of handheld appliances, such as smart phones, portable media players and GPS systems, are always looking for ways to extend battery life in their products. Complex Programmable Logic Devices (CPLDs) offer the flexibility to integrate random logic and specific IP functions in one low-power package.

Making CPLDs even more attractive to power conscious designers are several “Zero-Power” CPLD families that offer additional features to extend battery life. In handheld applications, programmable logic typically is used for random logic replacement, control or small data-path implementation circuits. CPLDs that combine very low power consumption and small form factors are ideal for these applications. Zero-Power devices from Lattice Semiconductor and other vendors boast a variety of innovative features to support designs for handheld appliances.

Techniques for reducing power consumption in CPLDs

Engineers have several ways they can architect their design to reduce power consumption, including lower clock speeds, bus terminations, low voltage operation, and bus-loading limitations. Even with these power-reducing techniques, however, the power requirements of conventional CPLDs often preclude their use in battery-powered devices. But now manufacturers of CPLD devices have introduced zero-power CPLD families.

“Zero-power” is actually a misnomer used by the industry, referring to non-volatile, instant-on advantages of CPLDs. What zero-power does mean is that the CPLD boasts a number of power saving features, as well as core logic that is designed to substantially reduce device power requirements in most applications.

These extended features include input gating and slew rate control. For example, a design with 32 inputs and 32 outputs toggling at 100 Mhz may consume 2.8 mA. However, using a zero-power CPLD, this same design consumes just 0.026 mA using the input-gating feature.

Input gating

Different vendors have different names for the input-gating feature (called “Power Guard” by Lattice Semiconductor). Input gating is an easy way to lower the operating power of the CPLD by disconnecting the logic array from external input signal changes. Any logic that changes state consumes power.

Removing the external stimulus activity from the logic array when it is not needed suspends internal logic activity. When input gating is enabled, the internal logic as well as the corresponding outputs maintain the state they were in.

The input-gating control consists of logic between the I/O pin and the input buffer. The gating logic is controlled by an output from one of the internal macrocells in the logic array (see Fig. 1 ).

The input-gating feature is enabled or disabled on a pin-by-pin basis. Some CPLD families provide one input-gating block for all the input lines, while others are architected with multiple blocks to provide precise control over individual sections of the I/Os.

Fig. 1. Input gating is an easy way to lower the operating power of the CPLD.

Slew rate control

Slew rate control provides each I/O pin with two settings for the output buffer state changes: fast and slow slew. Designs that use short traces or well-terminated lines can use the fast slew mode, which switches between states at the fastest rate and actually uses less power. For high-speed designs with long, unterminated traces, the slow slew mode will introduce fewer reflections, less noise, and keep ground bounce to a minimum.

Other advanced CPLD features

Other advanced features that typically are included in these very low power CPLD devices include input hysteresis, on-chip oscillators, and programmable termination. Input hysteresis provides improved noise immunity for slow transitioning input signals.

The newest CPLD families have very efficient I/O cells and full-time hysteresis on 3.3- and 2.5-V inputs. Less-efficient CPLDs allow the designer an option to disable the hysteresis function as a way to save power consumption in the I/O cell.

To help reduce overall system costs, advanced CPLDs now include an on-chip oscillator for a system clock. Typical uses for the oscillator include power up sequencing, keypad scanning and display controller applications.

Integrating the oscillator reduces the system device count and eliminates the cost of a dedicated oscillator. In designs that do not need the on-chip oscillator, the block can be disabled to provide additional power savings.

All zero-power CPLDs provide some form of programmable I/O termination for the input pins, in order to reduce power consumption due to externally tri-stated buses. Unterminated or floating inputs can use an inordinate amount of power as the signal strays in the area between the high and low standard logic levels.

Depending on which CPLD family is used, there are options for bus-keeper latch, pull-up, pull-down, or no termination (see Fig. 2 ). For example, Lattice provides all four modes, which can be assigned to each individual input pin.

Devices from other vendors provide the ability to implement the pull-up and bus-keeper options on a per-pin basis, or have global termination assignment for bus-keeper and pull-up, where each pin can be included or excluded from the termination group.

Fig. 2. There are options for bus-keeper latch, pull-up, pull-down, or no termination.

Each generation of handheld devices fits additional product functionality into a smaller space and CPLDs are an integral part of the solution. One reason is that they allow “quick fix” implementations for problems that occur in ASSP and ASIC devices. They also allow the integration of discrete logic solutions, and special functions such as memory controllers, interface bridges, LCD/touch screen interfaces, watchdog functions and power management.

CPLD suppliers offer zero-power devices in a wide variety of cost-effective packages ranging from 5 x 5 mm to as large as 28 x 28 mm. The number of available I/O pins ranges from 21 to 270 in a 324-pin BGA.

Chip-scale BGA packages provide the optimum ratio of I/O lines to package size, with the 64-macrocell ispMACH 4000ZE CPLD having 52 I/O lines in a 5 x 5-mm size (see Fig. 3 ). The CPLD also incorporates Power Guard input-gating control on the entire device family, which includes 2 to 16 segments in each device, allowing fine granularity in the power control.

An enhanced on-chip oscillator includes a divide-by-n timer module and full I/O support for pull-up, pull-down, and bus keeper that is enabled on a per-pin basis.

Fig. 3. A CPLDs with 52 I/O lines can come in a tiny 5 x 5-mm package.

During the power-up cycle, all the I/O pins are in pull-down mode, which reduces the current in-rush from the external signal lines. The CPLDs have typical standby power of 10 µA for the 32-macrocell device.

CPLDs can aid design optimization

As functional requirements continue to increase and additional interfaces are added to existing designs, zero-power CPLD devices can be implemented easily and keep the design within the system’s power budget. A recent review of a popular portable GPS receiver revealed several discrete devices used for interface and logic functions, including an SD card interface, bus transceiver, and port expander. These functions could have been integrated in one zero-power CPLD device, reducing the number of devices needed, lowering costs, and increasing overall reliability. ■

For more on CPLDs, visit http://www2.electronicproducts.com/DigitalICs.aspx.