Hardware-assisted verification platforms speed chip design

Hardware-assisted verification platforms speed chip design

Emulation-on-chip system can reduce development time by 25%

A family of hardware-assisted verification tools is said to deliver the industry’s fastest in-circuit emulation capability that facilitates concurrent hardware-software validation and embedded system verification. The Veloce Solo, Trio, and Quattro multifunction verification platforms for acceleration and emulation are based on a new emulation-on-chip architecture enabling megahertz-class verification run-time speeds without compromising debug productivity or modeling accuracy for designs up to 128 million ASIC gates.

The platforms are based on the System Verilog direct-programming interface and deliver up to 1,000X performance improvement over the fastest software simulator without compromising interoperability. The single-user Veloce Solo addresses systems up to 16-M ASIC gates in an acceleration or in-circuit emulation mode, while the Trio series provides transaction-based acceleration and plug-and-play event-accurate simulation acceleration and handles embedded system verification. The Quattro version addresses larger designs.

The new emulation technology delivers a three to five times boost in run-time performance compared to previous versions and yields compile times of up to 15-M RTL equivalent gates per hour. (Monthly rental, Veloce Trio, from $21,000 with 8-M gate capacityavailable now.)

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