High-level synthesis package speeds design

The Synphony HLS high-level synthesis package integrates M-language and model-based synthesis and is said to yield up to 10 times higher design and verification productivity than traditional RTL flows for communications and multimedia applications. The software creates optimized RTL for ASIC and FPGA implementation, architecture exploration, and rapid prototyping.

Synphony HLS complements C/C++-based flows by generating C-models for system validation and early software development in virtual platforms. It integrates with Design Compiler, Synplify Premier, Confirma, VCS, System Studio, and Innovator products for a comprehensive design platform. It also provides an automated flow from M-language code to optimized RTL, the synthesis of optimized RTL architectures, rapid prototyping methodology, and C-model generation for early software development. (Contact company for pricing — available now.)

Synopsys , Mountain View , CA
Information 800-388-9125
http://www.synopsys.com