Highly integrated clock ICs address optical networking challenges

Highly integrated clock ICs address optical networking challenges

Addressing complex timing requirements of high-speed optical transport network (OTN) applications, the Si5374 and Si5375 clock ICs are offered as the first single-chip timing ICs to integrate four independent PLLs, providing twice the PLL integration and 40% lower jitter — at 0.4 ps — than competing solutions. Based on company’s DSPLL technology, the parts produce up to eight low-jitter output clocks, simplifying the design of any-protocol, any-port 10G, 40G, and 100G OTN line cards.

Each DSPLL clock multiplier can be configured to generate any frequency from 2 kHz to 808 MHz from a 2-kHz to 710-MHz input. The Si537x devices can reliably lock to gapped clock inputs a critical OTN line card clock requirement without separate upstream low-bandwidth PLLs. Other carrier-grade features include SONET-compatible jitter peaking (0.1 dB max) and a hitless switching capability that minimizes output clock phase transients during reference switching, producing a 25x smaller phase transient than competing solutions.

Each DSPLL engine features a fully integrated loop filter that supports user-programmable bandwidths as low as 4 Hz. The parts are housed in 10 x 10-mm PBGA packages and operate from a single 1.8- or 2.5-V supply. (Ea/10,000, $39 to $59; Si5374-EVB/Si5375-EVB evaluation kits, $350 each — available now.)

By Christina Nickolas

Silicon Laboratories , Austin , TX
Information 512-416-8500
www.silabs.com