How to test high-speed memory with non-intrusive embedded instruments explained in white paper – Challenges an

How to test high-speed memory with non-intrusive embedded instruments explained in white paper – Challenges and tradeoffs of testing DDR3, DDR4 and other buses described in technical paper

Richardson, TX (July 24, 2012) –A new white paper from ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains how non-intrusive software-driven embedded instruments can overcome many of the challenges of testing, validating and debugging high-speed memory buses such the DDR 3 or DDR4 (DDR3/4) buses, and others.

The white paper describes the engineering tradeoffs involved with several non-intrusive test methods, including processor-controlled test (PCT), FPGA-controlled test (FCT), memory built-in self test (MBIST), boundary-scan test (BST) and functional test. The 21-page paper is written by Al Crouch, ASSET’s chief technologist for core instrumentation and vice-chairman of the working group developing the IEEE P1687 Internal JTAG (IJTAG) standard for embedded instruments. ■