IC design tool unifies C++ methods for algorithms and logic
The Catapult C Synthesis design tool for ICs and FPGAs delivers the first unified solution that lets engineers model, verify, and synthesize complex mixes of both control logic and algorithmic units from a single ANSI C++ source. The Version 2009a package also provides fully automated multilevel clock gating and interfacing to dynamic power and clock management units. The tool will analyze deep cones of logic to find gateable clocks, an otherwise error-prone and manual task, and yields, for an average design, a 40% power savings.
The package unifies control logic and algorithmic synthesis domains, traditionally addressed using different languages, formalisms, and abstractions, for faster, more-error-free designs. This innovation allows designers to easily specify asynchronous data communication, allowing full control over concurrent hardware creation, and interfaces algorithmic representations driven by the dataflow with control-dominated blocks synchronized by clocks. ($140,000 to $390,000 — available now.)
Mentor Graphics , Wilsonville , OR
Sales 503-685-7000
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