IC overvoltage protection

Devices such as SPAs, MOVs, and PPTCs are available to guard today’s integrated circuits

BY JIM COLBY
Littelfuse
Des Plaines, IL
http://www.littelfuse.com

Protecting ICs from ESD has become more difficult in recent years, mostly because of changes in chip design. At one time, ICs routinely included overvoltage protection, but as chip feature size shrinks, there is less and less room on the device for ESD protection.

Common solutions for protecting ICs against overvoltage events include MLVs, SPAs, and PPTCs.

Unlike logic circuitry, ESD protection is difficult to shrink, and the price of chip real estate has increased. At the same time, chip makers using improved ESD abatement procedures in the fab and assembly area—with ground straps, ionized air, and other means—have been able to build and package devices with good yield and low losses to ESD. However, it is still up to the application design engineer to provide the necessary ESD protection.

Fortunately, today’s protective devices provide all the protection needed fairly easily. Key selection criterion includes clamping voltage, size, and capacitance.

Multilayer varistors

MLVs are useful for both ESD and EMI protection. They’re available in capacitance values from 1 to 4,500 pF and in case sizes from 1210 down to 0402.

This is especially useful in handheld applications like cell phones, digital cameras, and MP3 players, where as many as 40 points require ESD protection between the keypad and the data I/Os. Operating voltages are from 3.5 to 120 Vdc, in single-line and quad-channel packages.

Silicon protection arrays

As array devices with multiple-channel packages, SPAs (also known as TVS avalanche diode arrays) can save board space on input ports where several lines are located closely together. This is especially useful for HDMI, USB, IEEE 1394, and Ethernet ports.

SPAs are available in sizes down to SOT 563, ideal for applications like cell phones, notebook computers, and portable multimedia players. However, their key advantage is that they have the best ESD performance of the three suppression technologies.

They turn on and clamp at the lowest voltage to minimize stress on the chip being protected. SPAs are available with capacitance values down to 0.65 pF and operating voltages from 5.5 to 30 Vdc.

Polymeric ESD suppressors

The key feature of these devices is their ultra-low capacitance value — down to 0.05 pF — which means they can provide ESD protection while maintaining signal integrity on high-speed data or high-frequency RF signals. This makes them a good choice for use on signal lines like HDMI, USB 2.0, IEEE 1394, and RF inputs on cell phones, satellite radios, and GPSs. For design flexibility, package options include single lines devices (0402 and 0603) and multiple-channel units.

The important specs

For an increasing number of ICs, peak and clamp voltage characteristics of the ESD suppressor are becoming more and more important in terms of effective ESD design. As a result of the findings of the Industry Council on ESD Targets in 2007, the level of on-chip ESD protection can be decreased from about 2 kV to 500 V, and in some cases even lower.

For chips that maintain robust on-chip protection, all three ESD suppression technologies offer good performance. However, for ICs that are extremely sensitive to ESD, it may be necessary to consider the SPA devices in order to pass system-level ESD tests like those found in the IEC 61000-4-2. ■

For more on circuit protection devices, visit http://www2.electronicproducts.com/Passive.aspx.