OL4.OCT RM Intel FPGA — Page
Intel to launch another entry in increasingly crowded FPGA market
Yet another twist on the FPGA theme has been announced, this one by
Intel. The par, to be sampled early next year, looks much like a MACH or
MAX complex PLD at first glance. However, it has significant differences.
Designated the iFX780, the chip has eight configurable function blocks
(CFB) joined by a fixed-delay global interconnect. The connection matrix
is fully connectable. However, the CFBs can each be either a
sum-of-products (24V10) or a 128 x 10-bit static RAM with a registered
output. The deterministic layout will have a 10-ns pin-to-pin propagation
delay. When a CFB is used as a PLD, it has 10 macrocells each with
internal and pin feedback paths. It has two asynchronous clear/preset and
two output-enable control terms, all with inversion option. One block can
implement identity-compare up to 12 bits, using the 24 inputs. The
comparator can output to any one macrocell. Each output macrocell has
four product terms except the two on the ends of a CFB, which have 14. Any
macrocell can borrow product terms in pairs from its nearest neighbors.
Thus interior macrocells can have a maximum of eight product terms, and
the end macrocells 16. The speed does not depend on the number of product
terms. When a CFB is used as static RAM, 7 bits of the fan-in are address
and 10 bits are data in. Three bits are used for block enable, write
enable, and output enable. A write cycle takes 15 ns. Nonvolatile configuration memory may be copied into a memory block at power on, making such
blocks usable as ROM if write-enable is not used. All active pins of the
iFX780 are linked in a JTAG 1149.1 boundary-scan scheme. Until nonvolatile
security elements are programmed, a prototype part can be debugged and
revised through the JTAG links without removing it from the circuit. In
production, the nonvolatile parts cannot be read out. I/O pins can work at
3.3- or 5-V logic levels. The chip uses about 1.5 mA/MHz up to the maximum
system clock of 80 MHz. It has power-down capability for portable
equipment, dropping to 5 mA with no clock. The usual vendors of software
and device programmers promise support for the iFX780 next year.
Meanwhile, Intel's PLDshell Plus, version 3.0 is available free for a
phone call. The software allows development, compilation, and simulation
of Intel PLDs, including the iFX780. In a 132-pin plastic quad flatpack,
the iFX780 , will be $55.35 each in lots of 100. An 84-pin plastic leaded
chip carrier will be $43.88 each, also in lots of 100. Samples are due the
first quarter of 1993.For more information, ask for literature packet
#IP-95 and the PLDshell Plus software, from the Literature Center of Intel
Corp., Santa Clara, CA, at 800-548-4725, or . –Rodney Myrvaagnes
CAPTION:
Inputs are all into the global interconnect matrix in the iFX780, while
I/O macrocells lead to pins as well as to internal feedback loops. In the
84-pin package, not all macrocells have pins, and the external inputs to the
global matrix are absent.
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