IP aids high speed video comm using Xilinx FPGA

IP aids high speed video comm using Xilinx FPGA

The SMPTE 2022-5/-6 intellectual property core is a building block for broadcast equipment developers using internet protocol-based systems to transport raw, high-bit rate video from remote events. The core makes use of forward error correction (FEC) and is capable of recovering IP packets lost to network transmission errors and ensure the quality of uncompressed professional video.

The SMPTE 2022-5/-6 video networking standard defines a transport protocol for the carriage of real-time, non-piecewise constant, variable bit rate MPEG-2 Transport Streams over IP networks. The SMPTE IP is deployable for designs targeting Virtex-6 or 28 nm Kintex-7 FPGAs with up to 32 high-speed GTX transceivers capable of supporting 12.5 Gbits/s speeds. (Price not given – available now.)

by Jim Harrison

Xilinx , San Jose , CA
Sales 408-559-7778
www.xilinx.com