IP cores target 3G+/4G wireless base stations

IP cores target 3G+/4G wireless base stations

Three key connectivity IP cores important for building 3G+/4G wireless base stations using Xilinx FPGAs are available. The LogiCORE IP cores for Serial RapidIO Gen 2 endpoint, JESD204 v1.1, and CPRI v4.1 are available in ISE Design Suite 13.3 and can be evaluated free of charge.

The SRapidIO core supports line rates of up to 6.25 G in 1x/2x/4x lane widths and comes with a configurable buffer design, reference clock module, reset module, and configuration fabric reference design. The Common Public Radio Interface (CPRI) aids connectivity between Radio Equipment Controllers or baseband/channel cards and the JESD204B v.1.1 .IP replaces wide parallel interface to data converters with 1/2/4 high-speed serial interface links to overcome I/O constraints. There are Design Suite logic, embedded, and DSP editions. (ISE Design Suite, Embedded Edition, node-locked license, $3,464; floating license, $7,098 — available now.)

By Jim Harrison

Xilinx , San Jose , CA
Sales 408-559-7778
www.xilinx.com