Critical analysis and design considerations to ensure optimal 25-Gbit/s performance
BY BRIAN HAUGE
Molex, Lisle, IL
www.molex.com
Data-transmission speeds are continuing to rise as consumers demand ever-higher performance from a variety of communications devices. New trends like cloud computing or Internet-based computing, where the need for seamless access to large data centers, are driving significant growth in bandwidth requirements. As a result, data networking and telecom infrastructure system designers are under growing pressure to create systems that will ease the transition from 10-Gbit/s speeds today to 25 Gbits/s over the next three to five years. All of the stakeholders in the physical link, which include the OEMs, active and passive component suppliers, silicon suppliers, PCB and/or raw cable suppliers, and contract manufacturers, must be willing to collaborate more closely than in the past.
Obviously, such a large-scale change creates major technical challenges. For example, the proliferation of high-speed and broadband systems in a range of industriesincluding telecom, datacom, networking, and a variety of other industrial and commercial usershas created the potential for significant signal-integrity issues. These issues range from traditional challenges like signal loss and noise, to newer areas like electromagnetic interference (EMI) and power integrity and efficiency. And as the system bandwidth demand increases for each of the high-speed serial links, the number of links (or ports) is also increasing. When both signal speed and port density requirements increase in the physical link, signal loss, cross talk, reflection, and mode conversion problems degrade system performance and become more challenging to resolve.
The good news for system designers is that there are more viable predictive analytical tools than ever before to minimize design risk and improve time to market for their products. These tools are used by component vendors to provide designers accurate and predictive component level models and end-to-end channel models to allow for the appropriate balance of price versus performance in their systems.
Price vs. performance
Commercial reality must be considered when upgrading data transmission systems. High-speed serial link system designers must balance each of the critical components’ price with its performance. If expensive, overdesigned components are used, the system can become too costly, and no one will buy it. Those components that ship with the system chassis (such as a blade server, core router or switch) must be upgradeable and scalable to 25 Gbits/s, but must also balance the costs of this scalability with the desired system performance.
Fortunately, new standards should make this component selection process easier. Industry groups such as the Institute of Electrical and Electronics Engineers (IEEE), the Optical Internetworking Forum (OIF), and the InfiniBand Trade Association (IBTA) are in the process of defining standards for 25-Gbit/s channels. These standards define pass/fail criteria and channel performance limits to help guide system designers.
It’s important that every component along the signal path be analyzed to determine its effect on the link’s performance. By electrically, mechanically, and commercially optimizing these channel components, better systems designs will result. Some of these channel components include the Tx/Rx silicon package and BGA vias, backplane and/or daughtercard PCB stack-ups and vias, mated connectors, dc blocking, etc.
Risk reduction
How can system designers be sure that their proposed systems will not only work, but be cost effective? There are three critical risk-reduction analyses they should employ to help ensure their investments produce an appropriate ROI:
• Link analysis.
• Power-integrity analysis.
• Electromagnetic interference (EMI) analysis.
There are predictive analytical tools and measurement techniques to evaluate each of these critical areas. This type of analysis is available from reputable industry suppliers. For example, Molex partners with industry leading OEMs and performs this analysis to ensure that all of the interconnect components in the channel are optimized for 25 Gbits/s.
Link analysis
Passive and active (silicon included) link analysis can help determine how each individual channel component affects the overall link performance. By performing a sensitivity analysis of each component, better price vs. performance decisions can be made.
Every data-transmission channel is unique, typically requiring proprietary design work. While standards can help guide the design, the real value of a data-transmission system is how well it performs the required task. Link analysis can help designers decide which components should be used to create an optimal, cost-effective, high-speed data-transmission system.
The good news is that predictive analytical tools for link analysis are getting better, having evolved and improved over the last decade. In the past, link analysis was typically passive, excluding the critical silicon components in the channel. Today, AMI tools allow for more generic platforms to analyze both the active and passive components in the channel, incorporating a menu of different silicon chips, PCB materials, connector solutions, etc.
Another benefit is that these generic active platforms allow system designers to compare the products of multiple silicon chip vendors, producing pass/fail “bit-error-rate” results for the link. That way, designers can avoid costly mistakes.
For example, when Molex engineers perform link analysis, they choose representative “corner cases” (unique cases that include multiple, worst case scenarios) to determine channel performance. We then run a passive channel analysis and perform a sensitivity analysis to determine the appropriate interconnect solutions, PCB materials, raw cable types, and design techniques. We then perform an active link analysis using these AMI platform tools to provide customers with BER values for their channels. The goal is to help designers minimize product design time and improve time to market.
Finally, component model and channel model correlation studies are performed. Molex builds prototype correlation platforms to measure corner cases to demonstrate that the models meet the measurements and will work in the field.
Power-integrity analysis
The second crucial analysis is PCB power-integrity. The increasing numbers of voltages used by ICs and dramatic increases in power consumption make it difficult to improve power integrity. Also, designers want to reduce layer counts (lower costs, improve via effects) and create finer pitch BGA footprints (port density) that perforate copper planes, but this makes it difficult to supply dc voltage and current. Achieving power efficiencies in 10-Gbit/s systems is difficult enough, so supporting 25Gbit/s systems will require particularly creative and novel designs.
Both modeled and measured sensitivity analysis are performed for each of the components in the link to ensure better price vs performance decisions can be made.
Driving signals to 25-Gbit/s speeds over long distances requires additional power. Also, power fluctuations affect the signal delay budget in silicon packages and can produce noise in the PCB. New modeling tools allow for board-level power integrity analysis, and other new tools can analyze power delivery and power distribution systems and their effect on system level thermal rise. These tools show “hot zones” in different mesh densities that could cause chips to overheat. The hot zones may require additional copper planes in the PCB or cabling to reduce heat load.
Emerging power and cooling technologies, coupled with optimized interconnect systems that support these higher current loads and increasing data rates, will likely prevail in the market.
EMI analysis
Electromagnetic interference analysis is the most challenging of the three areas. EMI (or RFI) is a disturbance that may interrupt or degrade an electrical circuit due to either electromagnetic conduction or electromagnetic radiation emitted from an external source.
Predictive analytical EMI modeling tools are emerging, but are not as far along as link analysis and power integrity tools. Therefore, EMI analysis still requires measurements of actual systems in EMI chambers. Since every data-transmission system is unique, each system must be analyzed and measured. For example, Molex components go through optimization studies that involve build/measure/model cycles that ensure optimal component performance with minimal electromagnetic emission.
Molex uses a custom variation of the SMART 1000 Mini-Reverb Chamber, built by ETS-Lindgren, to test hardware components. The test cell has dual chambers for transmit (noisy) and receive (quiet) applications. Each chamber has individual tuners driven by stepper motors that produce frequency ranges of 1 to 18 GHz, and 18 to 40 GHz. A floor (fully sealed) and ceiling (fully open) are determined, then the interconnect solution is tested to demonstrate EMI shielding effectiveness of a given design. This analysis helps to ensure that in the OEM’s environment, Molex solutions will provide adequate EMI performance. In some cases, the actual OEM’s system cards and/or chassis is tested in Molex’s EMI chambers to determine compliance.
This type of testing is critical in high-speed internal and external I/O applications, as well as some internal board-to-board applications. It is particularly important to minimize the potential effect of EMI inside computing devices. If a device emits large amounts of EMI, it may not comply with certain FCC standards.
Collaboration partnerships
It takes strong, collaborative partnerships among all of the stakeholders in the physical link to develop new components and solutions that enable 25-Gbit/s systems. Molex is focused on developing interconnect solutions through strategic partnerships to ensure the development of “complete solutions.” These partnerships are primarily with industry-leading OEMs, silicon vendors, PCB material houses, and contract manufacturers.
Today, the design tools and techniques to support best-in-class performance at 25 Gbits/s are available. Getting these products into service will take a cooperative effort among all industry partners. ■
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