Ivytown at the Solid State Circuits Conference

The ISSCC (International Solid State Circuits Conference) in San Francisco is even more crowded today than it usually is. In one session this afternoon Intel described their Ivytown server processor, which will be available late this year.

The FinFET, or Trigate in Intel speak, CPU has 4.31 Billion transistors on a 541 mm square die and has a 37.5 Mbyte cache and a package with 2,011 contacts. The device will also be available in 10 and 6 core versions, also.

The 15 core 3.0 GHz model takes only 130 W TDP. Intel's speaker, Stefan Rusu, also detailed the power consumption as 66% in the cores, 21% in the “uncore” (I guess the ring buses), 12% in the I/O, and 1.4% in the PLL and DTS circuits. Active power is 78% and leakage the remaining 22%.

The Ivytown I/O is interesting. There are 40 lanes PCIe Gen 3 at 8.0 Gbits/s, four lanes of Direct Media Interface (DMI) at 5.0 Gbits/s, 40 lanes Quick Path Interconnect (QPI) at up to 8.0 Gbits/s.

Plus, the chip has a new memory interface, the VSME (Voltage Mode Single Ended), which is configured with 72 pins (8 data + 1 ECC bytes). It uses a bi-directional interface with an Extension Buffer (MXB) – each buffer has one VMSE channel and two DDR channels. VMSE runs on the same pins as DDR3 for common die and provides ~75 GBytes/s four-channel effective bandwidth at 2667 MT/s/lane.