Lattice Semiconductor Expands Its Revolutionary ispClock Family with Programmable, Zero-Delay Clock Generator Devices

Lattice Semiconductor Expands Its Revolutionary ispClock Family with Programmable, Zero-Delay Clock Generator Devices

Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced its new ispClock™ second generation family of enhanced zero-delay clock generators, the ispClock5600A devices, along with the availability of the first device, the ispClock5620A. The programmable, E2CMOS® -based ispClock5620 devices can generate up to 20 clock outputs, each with independently programmable output skew, I/O standard and frequency selection.

Supports DDR II, QDR II and Many Telecom Clocking Applications.
Ideal for Clock Generation and Distribution in Backplane Line Cards

Heading the list of significant enhancements, the maximum VCO operating frequency of the ispClock5600A devices has been increased to 800 MHz. This supports the generation of popular clock frequencies such as 33.33MHz, 100 MHz, 133.33 MHz and 50 MHz simultaneously from a single master frequency. The input clock frequency range has been extended (5 MHz to 400 MHz) to enable support at 8.192 MHz, a popular telecom clock frequency. Additionally, the device's Universal Fan-out Buffer is able to source clocks to DDRII and QDRII memories (up to 400 MHz).