OL3.JUN–Mips Technology–RM
Low-power Mips processor has plastic package, power management
Chip aims at portable computers, laser printers, and other cost/power
sensitive designs
Mips Technology has taped out the R4200, a new design expected to
dissipate only 1.5 W running full tilt. Pin and code compatible with the
R4000PC, it has simplified initialization with fewer options and no
provision for multiprocessing or external cache.
Mips Technology (Sunnyvale, CA) will soon be sampling the most
mass-market-oriented of its Mips processors yet announced. The 3.3-V R4200
microprocessor will offer approximately 55 SPECint 92 performance at 40 or
80 MHz, comparable to a 60-MHz Pentium. In a plastic package, it will have
a volume price projected to drop to the $60 range by 1995. The R4200 will
run shrink-wrapped Windows NT, since it is code compatible with the
small-pinout R4000PC. It will come in a 208-pin plastic QFP (R4200LP) or
in a 179-pin ceramic PGA (R4200PC) for pin compatibility with the R4000PC.
The R4000PC pinout does not include internal support for a secondary
cache. SPECint ratings in the 50s depend on an externally managed
secondary cache much like those in 486 PCs. The R4200 on-chip caches are
16 Kbytes for instructions and 8 Kbytes for data. To reduce the power
dissipation and chip size, four-transistor cells are used in the caches
and dynamic logic is used throughout. A low-power mode drops the external
clock to 10 or 20 MHz, but the clock cannot be stopped completely without
saving the state registers. However, the reduced configurability of the chip
means there is less to save. Indeed, reset need only be held for 16 clock
cycles to load configuration registers from a serial EPROM. Perhaps the
most unusual design trick employed in the R4200 is possible only with a
64-bit processor. Specifically, the same data path and five-stage pipeline
serves both integer and floating-point operations. This entails many
pipeline stalls that would not occur in an R4000 and accounts for the 30
SPECfp projection. The relative integer/floating-point performance of the
R4200 puts it in PC, not workstation, country, but 30 SPECfp in a notebook
would be gratifying. The five-stage pipeline (vs.eight in the R4000/4400)
reduces the maximum clock, but cuts silicon as well. Other sacrifices
include reducing the TLB from 48 entry-pairs to 32 and cutting the
physical address space from 36 to 33 bits. In addition to the motherboard
sets currently available for the R4000 family, Mips engineers have devised
an ASIC that translates the microprocessor signals into those of a 486.
They have implemented the design with PALs and booted Windows NT on an
R4000PC mounted on a standard 486 motherboard with an Opti chipset. The
PAL design is now being converted to a gate array, which will be made
available soon. Fabrication of the R4200 is in the same process as the
R4400, already in production and tuned. With 0.6-micron features, triple
metal, and double poly, the chip measures 9.2 x 8.8 mm, compared with 11 x
11 for the Motorola MPC601 (see page xxx [lead ICNP]) and 7 x 12 mm for the
Intel i486 DX2/66. Motorola's chip, also 0.6 microns, uses four metal
layers and achieves 1.4 times the transistor density of the R4200. The
design of the R4200, partly financed by and first offered by NEC
Electronics (Mountain View, CA), is based on a core that can be cut and
used in ASIC designs (see diagram). It is expected to be useful in laser
printers and X terminals in dedicated forms. The other Mips silicon
partners are not required to make the R4200, but any may do so. NEC
expects to sample early this summer and should be in production this year.
For more information from NEC, call the Literature Hotline at 800-366-9782
or .
–Rodney Myrvaagnes
CAPTION:
By combining the floating-point and integer parts in a single data path,
the R4200 has a processor core less than half the area of the 9 x 9-mm
chip, small enough to combine with dedicated functions in an ASIC.
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