The SN65LVDS822 FlatLink LVDS receiver is said to be the industry's first to accept a lower pixel clock, enabling 30% longer video transmission distance, with 60% fewer wires and reducing EMI and power consumption. The chip has five receivers: 4 data and 1 clock and targets printers, cameras, and appliances with small LCD displays.
The receiver handles pixel clock rates from 4 to 54 MHz to enable panel resolutions of 160 by 120 (QQVGA) to 1024 by 600 (WUXGA) at 60 f/s with 24-bit color. It has several unique features, including three output slew rates, output voltage support of 1.8 to 3.3 V, a pin-out swap option, a configurable differential termination, and an automatic low-power mode. The 48-pin QFN packaged device costs $2.81 ea/1,000 and an eval module is available.
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