Managing power through the multicore revolution

As consumers continue to demand new functions and increased performance from devices such as smartphones, tablets and PCs, multicore processors have superseded traditional single-core devices. The latest families of multimedia application processors from leading vendors implement advanced architectures such as the ARM Cortex-A9 or Cortex-A15 core, and cover a broad performance spectrum with single, dual or quad-core variants. The launch of ARM’s asymmetrical big.LITTLE system builds on the multicore philosophy and also moves it forward, optimising power efficiency across all processing loads by combining a high-performance core such as the Cortex-A15 with an extremely energy efficient and architecturally identical core such as the Cortex-A7.
The emerging families of multicore application processors also integrate peripherals such as the DRAM controller and a media/graphics co-processor like the ARM Neon, which deliver further performance gains.

Power management evolution
When dual-core application processors entered the market, around 2011, the power architecture typically used with single-core devices was simply extended to power both processor cores from common supply rails. As the multicore roadmap has progressed, with quad-core devices already in the market, reports of octo-core devices in development and the prospect of even more complex processors in the future, extra flexibility is needed to control power to the cores individually to help optimise energy efficiency. This calls for extra complexity in the power management architecture, separating each core into its own power domain supplied by an individual regulator, as shown in Fig. 1 . This approach allows the use of smaller regulators, sized to supply a lower worst-case current demand.
 

Fig. 1: Separating cores into individual power domains enhances flexible and energy efficient power management.

Another important factor driving changes in the power architecture of multicore systems is the adoption of deep nanometre fabrication processes at 40-nm, 32-nm, and, more recently, 28-nm nodes. These cannot support the 5-V battery voltage (VBAT) connected to the input of each regulator, as smaller CMOS feature sizes demand lower operating voltages effectively reducing the maximum voltage that can be applied. For this reason, it is now necessary to migrate the power management functions out of the application processor into a separate device. This contrasts with the approach taken in first-generation mobile devices, in which power management was typically integrated with the application processor in a single-chip implementation.
With the trend towards a more complex multi-regulator architecture, implemented off-chip in a separate device, a new generation of more advanced and sophisticated power management ICs (PMICs) is emerging. The features and capabilities of these PMICs are evolving to help improve energy efficiency across the numerous usage modes of today’s consumer mobile and multimedia products. Typically, multiple switching regulators are implemented including buck regulators to supply low voltages such as the processor core and I/O voltages (which can be as low as 1 and 2 V, respectively, for processors fabricated at 28 nm), memory ICs and other peripheral devices. A boost converter may also be implemented for supplying LED strings such as the screen backlight. In addition, integrated low dropout (LDO) regulators can be used for powering important subsystems such as sensors, indicator LEDs or motors.
A variety of battery charging functions may be implemented, from a small power supply of a few milliamps for charging a backup coin cell or super-capacitor to a digitally controlled multi-mode lithium battery charger capable of connecting to a variety of sources such as a wall charger, USB 5-V supply or a car charger.
Additional features such as an analog/digital converter for monitoring external voltages and temperature may also be available. Moreover, power supervision and control intelligence implemented on-chip allows the PMIC to handle important functions such as power-up/power-down sequencing, reset generation and interrupt handling. This can help designers improve overall system reliability and energy efficiency.

PMIC in focus
As an example of the emerging generation of PMICs optimised for multicore applications, the DA9063 from Dialog Semiconductor has six buck regulators which operate at a fixed 3-MHz switching frequency. This allows the use of 1-µH inductors that are only 1-mm high, thereby supporting ultra-low-profile dimensions for mobile devices while allowing the regulators to supply high peak-current demands. Dynamic voltage control (DVC) allows adaptive adjustment of the supply voltage according to the processor load. Three of the buck regulators are capable of supplying up to 2.5 A, while the remainder deliver up to 1.5 A. Connecting regulators in parallel creates 5 A or 3 A rails to satisfy the core-current demands of today’s highest performing processors. Hence designers can scale or adapt the configuration to suit a variety of system requirements.
There are also 11 programmable LDO regulators, with output current ratings ranging from 100 to 300 mA. Support for remote capacitor placement and operation from a low input voltage of 1.5/1.8 V allow cascading with a suitable buck supply to improve overall system efficiency. A number of the LDOs can also be configured as current-limited bypass switches to support other peripherals such as memory cards or externally connected accessories. Moreover, some are optimized for low-noise applications, and one can be configured as a 6-bit PWM-controlled vibration motor driver for implementing haptic user controls.
The block diagram of Fig. 2 illustrates the six buck controllers, 11 LDOs, backup battery charger, and power-management and supervisory functions integrated in the DA9063.

Fig. 2: Power supply and management functions integrated in the DA9063 PMIC from Dialog Semiconductor.

 Improving system efficiency
Consolidating voltage regulators and intelligent power management functions in a separate PMIC such as the DA9063 provides the opportunity to implement a number of power-saving features that operate autonomously without intervention from the application processor. The power manager block has a startup sequencing engine that allows programmable start-up of internal and external regulators and rail switches. The PMIC has multiple operating modes including five low-power modes that draw as little as 20 μA or lower, which give designers extra flexibility to minimise system power in all usage scenarios. Among these is a 1.5-μA real-time clock (RTC) mode with alarm and wakeup, allowing the system to operate in deep sleep with very low power consumption. Also, by using the PMIC’s rail-switch controllers to drive external FET switches, designers can reduce the leakage current from cores that are powered down.
In addition, on-key button press detection allows configurable key-lock and application shut-down functions according to button press time. GPIO pins enable designers to implement many other power-saving functions including keypad supervision, application wake-up and timing controlled enable of external regulators, power switches or other ICs.
Inside the PMIC, dynamic voltage scaling in one or more switched-mode power domains helps to optimise processor energy per task, leading to higher efficiency. In addition buck quiescent current and LDO dropout voltage are generally low compared to similar discrete solutions. This not only enhances efficiency but also lowers internal power dissipation.
Integrating the lithium battery charger in a PMIC can deliver even more significant power savings. The extra efficiency of a switching charger with intelligence to track the battery charge can reduce internal power dissipation by more than 80% in a1.3-A/5-V implementation.

Impact on future generations

PMICs such as this enable the latest consumer multimedia products to achieve the performance increases needed to deliver the experiences today’s buyers are demanding, while using battery power efficiently to achieve acceptable recharge intervals. In addition, a PMIC is essential for simplifying power distribution to the growing number of subsystems such as dual high-megapixel cameras, multiple radios supporting Bluetooth, Wi-Fi, NFC and 3G or 4G LTE cellular wireless links, and various LED strings for lighting and status indicators.
Migrating power management from the baseband/application processor into a separate PMIC also provides greater freedom for designers to satisfy market demands for features such as larger screens with capacitive multi-touch control, and improved audio capabilities such as better speakerphone performance and high-definition audio playback. Some PMICs, such as the DA9059, integrate the audio subsystem comprising DSP, codecs, class-D speaker amplifier and class-G headphone amplifier in a single chip. This can yield bill-of-material savings of around 43%.
In the future, devices such as 4G smartphones are expected to drive this architectural trend even further forward by implementing two complex PMICs serving the baseband and the application processor individually.