Microchip makes a case for FPGAs in intelligent edge designs

Aimed at speeding up intelligent edge designs, Microchip Technology Inc. has added 10 technology- and application-specific solution stacks to its mid-range PolarFire FPGAs and systems-on-chip (SoCs). These solution stacks target the industrial edge, smart embedded vision and edge communication and include IP, reference designs, development kits, application notes and demo guides.

The one thing FPGA manufacturers have faced over the years is the complexity of programming FPGAs, which has stalled adoption in many applications. This is despite the FPGA’s key advantage of offering the capability for AI algorithm acceleration, custom design and reprogramming for new requirements.

Cost has also been an issue, but there are specific applications where FPGAs deliver advantages over other processors like microcontrollers (MCUs), microprocessors (MPUs) and graphics processors (GPUs). However, over the years, FPGA manufacturers like Microchip have made advances in cost reduction, making the FPGAs more power-efficient and smaller.

Microchip’s new solution stacks and software development kits (SDKs) are addressing these issues and are making it easier to design with FPGAs while enabling better collaboration between computer engineers and FPGA designers.

Why is Microchip coming out with these tailored designs for the intelligent edge? One of the big reasons is demand, and for sure, the company wants to be a leader in the intelligent edge. The other reason is to drive the adoption of FPGAs.

“We need to be more approachable as a technology, and that’s why we are offering the solution stacks,” said Shakeel Peera, vice president of strategy for Microchip’s FPGA business unit.

Microchip claims 32% year-over-year growth for its FPGA business, driven by its PolarFire mid-range flagship FPGA platform.

Peera said PolarFire is the fastest-growing FPGA platform in the company’s 35-year history (starting out as Actel in 1985 and later acquired by Microsemi in 2010 and Microchip in 2018). Now in its fifth year, PolarFire has grown 90%.

What is driving this growth is the intelligent edge, Peera said, with 65% of Microchip’s top 20 PolarFire customers in this space. Intelligent edge growth is across industries, including industrial edge, 5G/data networks, AI/ML in IoT, diagnostics in medical imaging, autonomous vehicles, military/aerospace and space compute.

FPGAs are well-suited for intelligent edge applications because of their flexibility. These applications are highly specialized, with diverse architectures and constantly evolving algorithms.

These applications are driven by the need to generate data and process data on the edge as opposed to doing it in the cloud and data center, Peera said.

What has happened over the past decade or so, and more recently, is that much of this processing will be done locally on the edge device, he added.

One example cited is advanced driver-assistance systems (ADAS), which require low latency. It does not work without processing on the automobile itself, Peera said. “It has to be innately low-latency, so that processing has to be done locally and the decision has to be made locally.”

Other examples include 5G networks that enable low-latency communications between devices, Industry 4.0+ or industrial automation, medical imaging and IoT.

Why FPGAs for the intelligent edge?

Processing elements today are usually serial processing units—GPUs, MCUs, MPUs or CPUs—and FPGAs perform processing in parallel and process more efficiently than a serial processing unit, Peera said.

AI/ML is applied to a variety of architectures—facial recognition, license plate recognition, security, thermal imaging, etc.—and FPGAs are very good at supporting diverse architectures because they can be reprogrammed over time, he added. “So when there are highly specialized applications that need acceleration, FPGAs are very good at that.”

However, Peera also made it clear that engineers have many choices, and depending on the problem that they are trying to solve and the performance needed, it will dictate which processor platform they will use.

PolarFire FPGAs and SoC FPGAs

Microchip is positioning itself in the market on power efficiency. The PolarFire family offers twice the power efficiency of FPGAs in its category with the highest reliability and military-grade security, according to the company, and are the first and only RISC-V SoC FPGAs shipping in production volumes. The PolarFire SoC devices create new configurable processing capabilities, targeting power-sensitive intelligent edge applications.

Intelligent edge designs have special requirements. Edge devices are usually not big systems, Peera said, and are small box-like systems that are remotely deployed in areas that are not in the central office.

So right out of the gate, thermal constraints and minimal power budgets are unique needs, he added.

Microchip’s PolarFire devices, compared with the competition, can perform the same workload at approximately half the power on average, though it varies between 30% to 70%, according to Peera.

This is related to thermal-efficiency cost in competitive devices. From a monetization standpoint to remove the heat and for the system to work correctly, Microchip’s studies show that it costs about $1.50/W, Peera said.

Also, with high leakage current, thermal runaway becomes a problem, Peera said. “At some point, your device will fail if you overburden it, so you will have to be very careful with how much processing is done in the chip.”

Microchip’s PolarFire devices inherently offer lower leakage current thanks to the use of non-volatile (NV) memory. “With the lower leakage current, the thermal runaway ceiling is lower, so you can do more processing, and this relates to how many dollars saved because you are doing more compute on a single chip,” Peera said.

NV technologies are innately lower leakage, he said, and the static leakage current of the PolarFire FPGAs is one-tenth that of volatile SRAM used by other FPGA vendors. “This gives us an advantage that the competition cannot overcome.”

Security is also becoming a big concern, which will only get worse with quantum computing that will be able to break asymmetrical cryptography, Peera said.

The two big concerns are intellectual-property protection and information assurance, he added. “Intellectual-property protection means that someone is not stealing your IP from your FPGA and then cloning it, and data security means that when your chip is talking to the outside world, that information as it gets transferred from Point A to Point B is assured and no one hacks into it.

“There are tons of cryptographic elements that can be put in software, but it doesn’t matter if your device can be physically tampered with,” Peera added.

Working with the U.S. DoD for more than 30 years, Microchip’s FPGAs have secure hardware built in, including NIST-certified cryptographic accelerators, physically unclonable function and built-in tamper detectors. Also, quantum-resistant authentication is on the roadmap.

In addition, there is a need for zero configuration failures in areas that have critical infrastructure or have high-radiation environments, Peera said.

Microchip’s FPGAs are immune to radiation effects, which is becoming a problem in terrestrial systems, he added, such as smart grids, data storage, communication infrastructure and safety-critical applications beyond aerospace systems.

This is where NV memory technology delivers an advantage.

A high-energy radiation particle can flip an SRAM bit – change the state of the SRAM cells – because the programming levels in terms of voltage are very low and can be flipped easily, Peera said, whereas NV technology is programmed at higher voltage levels and the bits cannot be flipped.

Together, these benefits translate into military- and aviation-grade security and reliability for the commercial marketplace.

Most importantly, the platforms need to do two things, Peera said: “One is to have heterogeneous compute architectures with FPGA signal-processing units or microprocessor subsystems [MSS] that all are available to the user and are able to compute in real time because low latency is very important on the edge.

“We’re able to offer heterogeneous compute platforms that can do a variety of processing, whether it’s an operating system with deterministic accelerators or something that you program in bare metal code,” he added. “Everything is available as a monolithic solution inside one FPGA platform.”

In addition to the technology benefits, using the open-standard RISC-V for its PolarFire SoC FPGAs gives Microchip the ability to innovate a lot easier and quicker.

Peera said the company took a big risk at the time to choose RISC-V over Arm, and there was a lot of debate on whether they should do it.

Once the decision was made to move to RISC-V, Microchip developed an architecture that delivers lower-power, highly flexible caches, asymmetric processing capabilities (using quad-core 64-bit RISC-V processors), real-time bare metal and RTOS on a monolithic MSS platform in a very small form factor.

Making FPGAs more accessible to computer engineers

FPGAs are very power-efficient accelerators, Peera said, but to program and design with them, engineers need to have an innate knowledge of custom hardware.

This means that you have to be an ASIC or FPGA designer.

The problem is that algorithm designers are not ASIC or FPGA designers; they are computer engineers who have learned to devise algorithms in C/C++, which does not enable custom hardware development, Peera explained.

“So how do you make FPGAs more approachable to computer engineers, which is an ongoing debate in the industry? People love FPGAs, but they end up designing with GPUs, CPUs and MCUs because they only have to design in C/C++ and they do not need to understand the underlying custom hardware, which is what FPGAs are,” he added.

So Microchip picked three hot areas—computer vision (or smart embedded vision), industrial edge (or industrial automation) and edge communications that are “completely sacrosanct to the intelligent edge”—to speed development and design time while meeting some of the biggest challenges, including power efficiency, security, latency and size.

“These are the leading killer apps for the intelligent edge, Peera said.

There is a lot of buzz around generative AI, but it is still in its infancy, he added. “What drives monetization is machine vision.”

Industrial edge encompasses areas like robotics, picking technologies and factory automation, and underpinning all of this is edge communications, so all of the systems talk to each other, including everything from optical data networks to 5G O-RAN, Peera said.

Although these solutions are a good start, computer engineers program in C/C++. The standard language for FPGA programming is Verilog hardware description language (HDL) or VHSIC HDL (VHDL).

Microchip offers its own high-level synthesis of C/C++ for FPGAs, called SmartHLS, that allows the engineers to easily use their algorithms for FPGA design by handling the software/hardware partitioning, compiling the MSS and hardware code and programming the FPGA. The benefits include a faster design cycle and fewer lines of code, and there is no need to completely understand the underlaying hardware.

“Schools aren’t producing a lot of electrical engineers for FPGAs; we’re producing a lot more computer engineers, and that is just the fact of life in the United States,” Peera said.

“So the FPGA designer is a rare commodity,” he added. “The idea here is to make the collaboration between the computer engineer and the FPGA designer much easier. Not all computer engineers will be using FPGAs as a de facto standard, but FPGAs are good at certain things.”

The solutions are architected so the computer engineer can handle the AI/ML algorithms and hand it over to FPGA designers in a manner that they understand, Peera explained, adding that this makes FPGAs approachable but in a collaborative design environment.

FPGAs offer a blank slate, Peera said. “If you have 80% of the algorithms done but need to work on 20% that is something new, FPGAs are awesome for that and have a place in new emerging chaotic segments, and today, it is AI/ML.”

The solutions

The PolarFire FPGA intelligent edge solution stacks target specific technologies and vertical markets: smart embedded vision, industrial edge and edge communications.

The smart embedded vision stacks encompass H.264 compression, HDMI, serial digital interface and CoaXpress. They deliver a variety of options for sensor and display interfaces, encoding/decoding, image processing, DDR controllers, transport interfaces and deep-learning inference (via the VectorBlox SDK).

Embedded applications, such as augmented reality, medical vision, surveillance, thermal vision and virtual reality, are driving the monetization of AI/ML at very high resolution—4K to more than 8K—and the common factors are that they are very small and low-power and need to be thermally efficient, Peera said.

The pre-made solution stacks and SDKs make the porting of the algorithms needed for embedded vision very easy and include everything from post-sensor processing to distributing that processed image to the display, network or robotic arm, etc., and right in the middle is deep-learning inferencing, he explained.

These are building blocks that make it easier for the designer to start their designs, providing total system solutions that not only provide the FPGA but also its underlying solution stacks and the solutions around it, Peera said.

Industrial edge focuses on motor control and Open Platform Communications/Unified Architecture (OPC/UA). Edge communication targets software-defined radios, USXGMII, small form-factor pluggable (SFP+) optical module and 5G O-RAN.

The motor control solution is comprised of IP blocks and algorithms for the PolarFire devices and the SmartFusion 2 Classic FPGAs; a dual-axis motor control kit; asymmetric processing with the PolarFire SoC; and software, programming and debug to optimize the design. The OPC/UA industrial edge solutions include a PolarFire SoC video kit for smart-camera applications and an Icicle Kit that controls a stepper motor. Both run on an OPC/UA server on Linux. A host Windows PC runs UA Expert, a Windows OPC client.

OPC/UA is one example of an open industrial bus, Peera said. This open network offers the capability to plug-and-play several solutions—remotely joined together, leveraging the FPGA’s flexible I/O, he added.

The edge communications solution offers a range of building blocks. These include data aggregation/bridging, encoding/decoding, transport interface, Ethernet MAC, and DDR controllers and optical module interfaces. Along with the PolarFire SoC FPGA, Microchip supplies the PoE PD, power/LDO, MEMS oscillator and 1G/10G PHY.

SDKs are also part of the new solutions. One example is the VectorBlox Accelerator SDK for ML inference of PolarFire and PolarFire SoC FPGAs. It offers 2× to 3× greater power efficiency compared with mid-range SRAM FPGAs, according to Microchip. Key applications include facial recognition and license plate detection.

The expanded solution stacks follow the June announcement of an industrial edge stack for OPC/UA and new resources. Future solutions include AI/ML/image processing, high-speed connectivity, security and compute-oriented software design kits.

Microchip also gave a sneak peek into its second-generation PolarFire FPGAs, which will double the power efficiency again, for a 4× improvement. They will also offer deterministic and asymmetric processing; military-grade anti-tamper and cybersecurity; and immunity to SEUs.

All PolarFire devices are in full production. Developers can access the software tools here.