Mid-range FPGA family cuts power by 40%

The Arria 10 next-generation mid-range FPGA family features a 40% active power reduction along with a 15% performance improvement. The 20-nm devices logic clocking goes from 300 to 500 MHz, and I/O bandwidth is raised due to sixteen 28 Gbit/s transceivers and 17.4-Gbit/s backplane support.

The family has from 160 K to 1,050 K logic elements and 156 to 1,581 DSP blocks, with up to 53 Mbytes of 64-bit DDR4 memory. The SoC versions have a dual-core Cortex-A9 processor, which now runs at 1.5 GHz. PCI Express Gen3 x8 is available as a hard IP. Versions come in packages ranging from 19 x 19 to 45 x 45 mm. Samples will be available in early 2014.