MS85.OCT–Texas Instruments–SC
Military multichip modules need `perfect' die
Obtaining semiconductor die without defects challenges MCM makers and
users as packaging technology grows
BY TOM POWELL and DUDLEY GAGE Military Products Div. Texas Instruments
Inc. Midland, TX
The military is actively looking at multichip modules as a means of
overcoming density and performance limitations that hamper present
packaging technology. Whether the military use of multichip modules
increases dramatically hinges on one key factor–the ability to obtain
virtually perfect individual silicon die to populate the MCM. The need
for known-good die–also known as KGD–is driven by both MCM cost and the
several means the industry has to test semiconductor die. With an
individual bare or packaged die, all interconnects are available for test
and evaluation. In an MCM, by contrast, many of the interconnects in the
individual die remain internal to the MCM and thus are unavailable for
testing. Consequently, finding part defects in the MCM is far more
difficult. For MCM yield, performance, reliability, and cost to be
acceptable, individual die yield must approach 100% (see diagram).
Moreover, as MCM technology increases in popularity, more manufacturers
will procure ICs for their modules from outside sources. The San Jose,
CA-based marketing research firm Dataquest has estimated that, by the turn
of the century, 33% of all chip production will be slated for installation
into MCMs and hybrid assemblies. No module manufacturer, even the major IC
suppliers, can manufacture all the diverse components required for complex
MCMs. These chips must be obtained in assembly-ready condition. They must
also be guaranteed to meet the same electrical and reliability
requirements as the equivalent discrete packaged component. A universal
definition for a KGD has not yet been established, but for most MCMs a KGD
must meet two requirements: 1. The die must be unpackaged and ready to
assemble in the MCM using the chosen manufacturing technique. 2.
Electrical performance and reliability must be guaranteed through
sufficient individual die pre-testing and conditioning. Besides these
basic requirements, the MCM manufacturer must consider other factors
before assembling an array of KGD in an MCM. Depending on the MCM process
used, these factors include mechanical specifications, processing
limitations, metal and passivation materials, and testability features.
To provide standardization for the burgeoning KGD industry, the Austin,
TX-based SEMATECH consortium, in conjunction with Microelectronics and
Computer Technology Corp. (MCC), Austin, TX, has formed a team consisting
of representatives from the major U.S. IC manufacturers to draft a KGD
specification for the industry. This draft will be presented to JEDEC in
an effort to generate an industry standard based on various MIL-STD and
IEEE specifications. The document will encompass the physical, electrical,
and reliability requirements the KGD should meet (see Table 1). In
general, the KGD specification aims to match the yield, performance, and
reliability of the individually packaged component to that of the die.
However, simply processing the die to meet the requirements of the
packaged product may often be difficult or impossible–and totally
unnecessary. Preparing a bare IC for full-temperature-range testing or
burn-in can be imposing. In most cases, the manufacturer has a wealth of
data including a device history to indicate the testing and processing
requirements needed to guarantee the performance, quality, and reliability
of a particular product. This data, rather than a rigid specification of
electrical and preconditioning procedures, should drive the selected
processing requirements for a particular KGD component. Such alternatives
as overvoltage stress, specification guard banding, device-fits history,
and boundary-scan and JTAG (Joint Test Action Group) testing of the MCM
can help eliminate requirements for burn-in and extreme temperature
testing, which are difficult to perform in bare die form.
Die evaluation techniques Several different techniques are in
development around the industry to test at speed, test at temperature, and
burn-in bare die. Techniques in varying stages of development include hot
chuck probing, tape-automated-bonding (TAB), temporary packaging via wire
bonds, temporary packaging via solder bumps, temporary package/carrier via
contact probe. Table 2 compares the performance and cost factors for
each of the die evaluation techniques. The key thing to remember is that
none of the present techniques provides a perfect solution. The costs
associated with the various evaluation techniques are in most cases
comparable to, or slightly higher than, those of conventional packaged
devices. Hot chuck probing is an extension of conventional wafer probing
procedures. It involves wafer probing performed at room or slightly
elevated temperatures with each dislocation on the wafer tested for
continuity, functionality, and limited parametric performance. Test
parameters include voltage and current levels at dc and sometimes low
frequency ac (1 MHz) conditions. Hot chuck probing would extend the wafer
level testing to full data sheet requirements at high temperature and
speed performance. The advantages and disadvantages of the hot chuck
probing approach depend upon device and technology. The cost of
implementing this approach increase with higher pin counts, higher
operating speeds, higher operating temperature, and longer test times. The
approach is well suited for mature technologies, particularly bipolar,
where burn-in may not be required. It can also be cost-effective for
low-pin-count devices, such as memory, where the cost of the probe cards
are significantly lower than for high pin count processors or ASICs.
Designing and producing probe cards for higher speed and higher
temperature testing can increase cost significantly, particularly for high
pin count devices. Tape-automated bonding is a technique that uses
devices which have been mounted in tape-automated-bond (TAB) leadframes to
facilitate the temperature testing, performance testing, and burn-in
processes. The TAB leadframes are excised from the die before final
assembly into the MCM. Mounting TAB devices in industry-standard test
carriers enables the IC manufacturer to perform test and burn-in using
industry standard hardware and procedures. The major advantage of the TAB
approach is its production maturity. TAB is in volume production in Japan
to support consumer applications and has begun to gain popularity in the
U.S. in recent years. Unfortunately, TAB incurs additional wafer-level
processing costs and high incremental tooling costs. And, only a handful
of the thousands of ICs are presently available in TAB format. Temporary
packaging via wire bonds utilizes standard packaging techniques to mount
devices for evaluation in a temporary, low-cost package using standard
wire bond processing. Like TAB, this approach is well understood and
presents a low-risk approach to testing at temperature, testing at speed,
and burn-in with standard test procedures and hardware. The principal
disadvantage of wirebonding, other than cost, is the damage done to the
die bond pad during the wire bond process. Typically, the die is removed
from the temporary carrier following die evaluation and placed in a
carrier. This leaves the heel of the wire bond on the die bond pad.
Techniques for creating an oversized or alternate bond pad have been
developed, but the non-planar die surface created by the wire bond remnant
creates a processing problem for some MCM approaches. There have been recent
reports of process development for removing this bond remnant, but the
practice is not currently in production. Temporary packaging via solder
bumps is similar to the wire bond approach, except that the die are
attached to the temporary package with solder bumps using a flip-chip
approach. The solder bumps can be placed on the die surface on the
original bond pads or on alternate bond pads that have been designed into
the circuit design or added via additional wafer processing. Following the
addition of the solder bumps, the die is attached with a flip-chip, solder
reflow process to a temporary package/carrier. Ideally, this package will
be in an outline that allows the use of standard test hardware for full
parametric testing, full temperature testing, and burn-in. This process
is well suited for flip-chip MCM applications. The residual solder or
foreign material left on the bond pads may present some processing
problems for other MCM approaches. Adding to the cost of this approach is
the special equipment required to align and attach the die to the
temporary carrier/package. Temporary package/carrier via contact probe
uses a temporary carrier or package with electrical contact made to the
die bond pads via a pressure contact. These pressure contacts can take
several forms including conventional probe type contacts, membrane probes,
and a pressure contact to a z-axis conductive polymer added to the die
surface to protect the surface. In this approach, films would usually be
removed from the die surface after die test and burn-in. Using a
temporary package appears to be the most universally appealing approach of
the techniques discussed. Unfortunately, it is also the least proven. As
with all technology development programs, the true costs will become
clearer as the process approaches production.
CAPTION:
To achieve acceptable final yield for the multichip module, the yield of
the individual die used must approach 100%. Unfortunately, as this graph
shows, increasing the number of individual die reduces the final module
test yield..
Table 1. Proposed JEDEC Known-Good Die Requirements
* Electrical Characteristics
* Reliability/Expected Life
* Sample Availability
* Mechanical Data (x, y, z) in a Standard Format
* Bond Pad/Passivation Opening Map and Dimensions
* Jumper Bonds
* Backside Surface
* Junction Temperature (maximum and minimum)
* Process/Device Limitations
* Metallization and Passivation Composition
* Backside Electrical Potential Requirements
* Testability Features
* Boundary Scan Language
* Wafer Fab Certification Status (QML, ISO, JAN, etc.)
* MIL-STD-883 Visual Change Notification
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