Multi benefits from multi-PLL programmable clocks

Multi benefits from multi-PLL programmable clocks

There are several different solutions for meeting the clock requirements for multimedia and consumer applications

Baljit Chandhoke
Product Line Manager,
Clock & Data Management
ON Semiconductor
www.onsemi.com

There are several different solutions for meeting the clock requirements in set-top box, digital TV, home gateway and consumer applications. Crystals and CMOS crystal oscillators have traditionally been used, and now multi-PLL programmable clocks can provide an alternative solution.

Set-top box, digital TV, home gateways and consumer applications have multiple clock interfaces; a clock is needed for USB, PCI, Ethernet, video, and memory interfaces, as shown in the set-top box example in Fig. 1 .

Fig. 1: Set-top box typical block diagram.

These clock interfaces support various functions. Table 1 shows the clock frequency for each application. As an example, for the USB interface either a 24- or 48-MHz clock is required. For the video interface, a 27-MHz clock is required, and PCI Express needs a 66-MHz clock.

Table 1: Clock frequencies commonly used in set-top box, digital TV, home gateways, and consumer applications

The problem with using discrete crystals and CMOS crystal oscillators is that these approaches require between five and seven crystals or crystal oscillators per product which can prove very expensive. Discrete crystals and CMOS crystal oscillators have no spread spectrum for EMI suppression, numerous devices are required, they also occupy considerable amounts of valuable board space and increase design complexity which may lead to lengthened time to market for new designs.

The primary benefits of multi-PLL programmable clocks versus discrete crystal and CMOS oscillators are that they reduce required board space and design complexity as one multi-PLL device is able to replace several crystals and CMOS crystal oscillators. They also cut total cost of ownership by between 30% and 50% (component BOM, PCB, and assembly costs).

By using I2 C EEPROM programming, Multi-PLL clocks are able to generate a wide range of frequencies. This flexibility allows designers to use a single device in multiple applications with different frequency requirements with the resultant benefits of shortened lead times and a reduction in the number of parts stocked.

Through a reduction in the number of parts required to satisfy a product’s clock requirements, additional functionality can be incorporated in the end product or further miniaturization of overall product packaging can be achieved. Multi-PLL programmable clocks also enable the synchronization of clocks to the same frequency reference or crystal input to avoid any timing mismatch in the system. Last minute clock changes can be easily implemented giving designers a “safety net” and greater flexibility. Other useful features include spread spectrum to help the suppression of EMI and a power-down mode that enhances overall system efficiency.

As example, devices such as ON Semiconductor‘s FS6370 (see Fig. 2 ) have three PLL clock generators with the capability to generate up to four CMOS clock outputs allowing them to replace up to four crystals or CMOS crystal oscillators. The I2 C EEPROM programmability allows designers to select frequencies at the early evaluation stages of a project or at the point of mass production.

Fig. 2: Block diagram of ON Semiconductor’s FS6370 multi-PLL programmable clock

Programmable clock multipliers such as ON Semiconductor’s NB3N3020 (see Fig. 3 ) provide 26 desired clock frequency multipliers per device. These can be factory programmed to meet customer applications and requirements enabling the replacement of many different clocks in different systems by a single, custom tailored clock. The programmable clock multiplier has one LV-CMOS output and 1 LV-PECL output with a wide output frequency range of 8 to 210 MHz. Programmable clock multiplier has excellent jitter performance with typical rms cycle-to-cycle jitter of 5 ps.

Fig. 3: Block diagram of ON Semiconductor’s NB3N3020 programmable clockMulti-PLL programmable clock solutions for set-top box, digital TV, home gateways, and consumer applications can overcome many of the problems associated with discrete crystals and CMOS oscillators. They can provide the opportunity to save valuable board space by reducing the number of components required to provide multiple clock sources.

The resultant reduction in component count and design complexity also leads to a significant reduction in BOM costs. Programmability also gives designers the flexibility to settle on a frequency at any point in the design process and use a single device across many product platforms. ■

References

Basics of Clock Jitter by Baljit Chandhoke, www.onsemi.com/pub_link/Collateral/AND8459-D.PDF