OL1.FEB–SC
Multichip modules stride toward greater acceptance
Technology shows signs of maturing as more chips become available in
multichip format
Several years after being heralded as the packaging technology of the
future, multichip modules appear to be finally living up to their intended
promise. The industry is starting to tackle obstacles like the
availability of known-good dice, testability, and the need for standards.
After a slow start, multichip modules are beginning to catch on as the
packaging technology of the 1990s. Users of multichip products and
services are seriously starting to accept and implement the technology.
However, like surface mounting, which was the packaging star of the 1980s,
multichip modules still face many obstacles. The obstacles include lack of
availability of known-good dice (see Electronic Products, October 1992, p.
41), testability issues, the availability of design tools, and the lack of
design and process standards. A daunting obstacle facing users of
multichip modules is their high cost. Up to now, most multichip modules
have been feasible only for costly high-end applications like mainframe
computers and military systems. But Motorola's Semiconductor Products
Sector (Phoenix) is trying to tackle this problem by offering multichip
modules for designers of cost-sensitive, low-to-medium power commercial
products. The company has announced that it will produce
application-specific ICs in multichip module form. Designated the MCML
series, the modules combine multiple ICs on a small pc-board substrate (see
photo). The ICs include not only as ASICs, but microprocessors and
memories as well. The combination of ICs and substrate is molded with a
plastic compound into standard EIA-J quad flatpacks. Motorola's
seven-layer module has an integrated copper leadframe to simplify
construction. Dice are connected directly to the leadframe to produce a
heat-transfer path. The multichip substrates are encapsulated in the same
molding equipment used for single-chip packages, and are compatible with
conventional semiconductor assembly and test equipment. Thus, they provide
a relatively cost-effective way for users to attain the density advantages
of MCMs. Other companies are extending their multichip-module fabrication
capability. For instance, IBM Corp. (Armonk, NY) has for years employed
multichip module manufacturing internally. But now, the company offers its
production capability to other users as well. IBM primarily bonds chips to
substrates using its flip-chip bonding technique. IBM has also signed a
manufacturing and licensing agreement with Irvine Sensors (Costa Mesa,
CA), to manufacture and ship Memory Short Stacks. The Short Stacks are
stacks of memory chips that are physically interchangeable with
single-chip packages yet are up to four times denser, with accompanying
performance benefits (see Electronic Products, July 1992, p. 21). They
make it possible to build even denser MCMs. IBM will manufacture the Short
Stacks for both itself and Irvine Sensors. Also offering stacked chips is
Dense-Pac Microsystems (Garden Grove, CA). The memory chip packager has
already applied its stackable chip carrier technology to 16-Mbit dynamic
RAMs (see Electronic Products, November 1992, p. 16). Now, it is making
available 128-K x 8-bit static RAMs in stacked-chip form for MCMs. Like
the company's other stackable chips, these parts come pretested and
screened–thus improving the all-important final stack yield so crucial to
reliable MCMs. The availability of fully tested bare dice for the chips,
commonly referred to as known-good dice, remains an important issue
because each individual die in a multichip module is internal to the
module. Any defective die renders the entire module bad–a costly
proposition. According to Jerry Johnson, marketing manager of Memory
Components for Micron Semiconductor, a subsidiary of Boise, ID-based
Micron Technology, the problem has been getting known-good dice at a cost
multichip module makers can live with. According to Johnson, that cost is
still prohibitive for makers of high-volume commercial products, but
within the reach of those making military/avionics and high-end commercial
products. For its part, Micron has recently began shipping production
known-good dice for its 128-K x 8-bit static RAMs. Other companies such as
Intel (Santa Clara, CA), National Semiconductor (Santa Clara, CA), and
Texas Instruments (Dallas), have also announced the capability to offer
known-good dice. But like Micron, the known-good dice are available at a
stiff cost. On a related front, Microelectronics and Computer Technology
Corp. (MCC), in conjunction with the Sematech consortium, both in Austin,
TX, is attempting to draft a known-good dice standard for the industry. A
draft of the proposed standard has been sent to JEDEC for review. Another
issue with MCMs has been the availability of adequate design tools.
Several well-known vendors of CAD software–notably Cadence Design Systems
(San Jose,CA) and Intergraph Corp. (Huntsville, AL)–have responded by
adding multichip module design capability in their software. More
recently, other CAD vendors have joined the fray. One of the most
complete design solutions for MCMs is a design kit jointly developed by
MicroModule Systems (Cupertino, CA) and Mentor Graphics (Beaverton, OR).
The kit includes MCM models, libraries, and technology files that include
manufacturing layout rules and off-the-shelf substrate definitions. The
design kit also includes information for layer structures, via sizes,
input/output pads, chip and wire bond pads, and physical layout analysis
models. A 55-MHz RISC CPU is used as a design example. The design kit is
designed to work with MCM Design Station, an integrated toolset from
Mentor Graphics that allows the user to customize layout, thermal
analysis, and signal integrity analysis of MCMs. MCM Design Station can
operate either independently or in the Mentor Graphics design environment.
Another recent software product for designing MCMs is Finesse MCM
Version 5.0 from Harris EDA (Fishers, NY). This multichip module software
adds new routing capabilities for the complex via structures required for
device fanouts in MCMs, as well as gridless routing. The software also
provides a dynamic logical/physical layer display that enables design
engineers to view MCMs either by logical sequence within the CAD system or
by the physical construct required during fabrication. The Finesse
software also offers a choice of process technology kits having design and
process rules that will ensure that the modules produced with the software
are manufacturable and compatible with foundries. Another MCM issue is
the choice of substrate interconnect technologies. Three major MCM
processes–ceramic (known as MCM-C), thin-film on silicon (MCM-D), and
laminate-based (MCM-L) exist. Of these, the laminate-based technology,
which is similar to that used to make pc boards, is the least expensive,
while the thin-film is the most expensive. Because all of these
technologies have advantages and disadvantages for different MCM
applications, it is not likely any one of them will predominate in the
near future. David Carey, a senior staff scientist at MCC, believes that
process improvements will eventually result in a blurring of MCM
technologies. “What will emerge are processes that combine the best
characteristics of each technology,” he says. For its part, MCC has been
actively looking at developing laminate-based MCM products, as well as
investigating the use of square instead of round silicon wafers to reduce
the cost of the expensive thin-film MCMs. –Spencer Chin
CAPTION:
ASICs are now available from Motorola in a multichip module format.
Designated the MCML series, the modules combine multiple ICs on a small
pc-board substrate.
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