Chipmaker Freescale Semiconductor (Austin, TX) recently announced an innovative multicore power architecture chip family that brings higher efficiencies and performance, and addresses the challenges of multicore software development. Dubbed the Multi-core Communications Platform, the 45-nm chip family will feature 50% lower power and a hypervisor environment that enables multiple operating systems to share system resources, including processor cores, memory, and accelerator cores. At the heart of the platform is a highly scalable fabric for on-chip connectivity that eliminates bus contention and latency issues associated with multicore shared-bus/shared-memory methods.
The platform’s hypervisor environment enables multiple operating systems to share resources.
The technology can seamlessly accommodate more than 32 cores. The platform will also feature cache-coherent hierarchy that endows each core with its own L2 cache and integrates multi-megabytes of shared L3 cache. The chip’s design tools provide virtualized software development that combines a fast functional model from Virtutech (San Jose, CA), called Simics, with a cycle-accurate model of the platform.
The platform’s simulation environment is expected to be available in the fourth quarter, and the first products based on the platform are planned to sample in late 2008. For more information, visit http://www.freescale.com
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Jim Harrison
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