Multimedia video processor to put multiprocessing on a single chip Processor is designed to handle all audio, video, and imaging compression-decompression standards A multiprocessor chip joins its elements, including memory, with a crossbar. The chip may be able to handle all multimedia applications through reprogramming, and eliminate several separate boards An ambitious start to a new processor series in the 320 line, the TMS320C80 multimedia video processor (MVP) will combine four digital signal processing sections and a master processor with a floating-point unit. Production is planned for 1995, and although limited samples are said to be available, at this writing a data sheet was not. The designation TMS on a Texas Instruments part number once meant a production part. What it means now is not clear. The following information was teased from a blizzard of hype and should be treated with caution. The highly integrated part joins its elements with a 32-Kbyte common memory via a crossbar switch (see photo). The connection includes the 64-bit-wide I/O transfer controller as well as the DSP sections and control. The transfer controller has a direct interface to external video RAM, dynamic RAM, or static RAM. The MVP also integrates 32 Kbytes of SRAM accessible to all DSP sections via a crossbar switch. The crossbar implements a round-robin rule to prevent two processors from accessing the same RAM in the same cycle. The shared memory is divided into 8-Kbyte sections, so as long as accesses don't conflict within a section, processing continues. The DSP processors have 64-bit instructions and a 25-ns cycle. The long instructions operate a 16-bit multiplier and a 32-bit arithmetic logic unit together. The multiplier can do one 16 x 16 or two 8 x 8 multiplies. The ALU can be split into two 16-bit or four 8-bit ALUs so lower-precision data can be handled faster. Each DSP section has a dedicated 2-Kbyte instruction cache, so the sections are not constrained to run the same instruction stream. The master processor, which Texas Instruments says is a RISC unit without qualification, has 32-bit words and instructions. It includes an IEEE-754 floating-point unit, and has its own 4-Kbyte instruction and data caches. The master processor can access 64 bits of data and a 32-bit instruction in one cycle. Its instructions include floating-point vector operations geared to image, audio, and 3D graphics processing. A suite of development tools is available now, for $30,000. The tools make use of on-chip emulation services through the JTAG port. About 9% of the real estate is devoted to emulation. The toolset includes software simulation, C++ compiler, high-level debugger, a device executive to manage scheduling, separate C compilers for the DSP and master processor sections, an assembler for the master processor, and an algebraic assembler for the DSP sections. Libraries of code should become available from Texas Instruments and third-party vendors. The chip is produced in the company's 0.5-micron CMOS DRAM process, and runs on 3.3-V power. It comes in a 305-pin ceramic PGA. Texas Instruments estimates initial production price will be between $300 and $400 ea/10,000. For more information call the Texas Instruments Literature Center at 800-477-8924, ext. 4500, or . –Rodney Myrvaagnes CAPTION FOR DIE PHOTO. The multimedia video processor counts 4 million transistors, including those in 50 Kbytes of on-chip SRAM. It will be produced on a 16-Mbit DRAM process.
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