New bus drivers carve out a broad path

MOTO.MAR–Motorola–RM– — –##

New bus drivers carve out a broad path

A guide to TTL-compatible bus interface offerings in popular 16 to 20-bit widths

BY GARY THARALSON
Motorola, Inc.
Phoenix, AZ

As bus widths have increased in recent years from just 8 bits to 16, 32, and even 64 bits, several vendors have introduced wider bus-interface devices. Not only must bus interfaces be wider, but they must also insert less path delay and minimize power consumption. These conflicting requirements have forced semiconductor manufacturers to use new technologies and submicron geometries. In addition, many of these new circuits incorporate features to deal with RF noise, electrostatic discharge (ESD), wide operating temperatures, live insertion and removal, bus termination, and automatic testing.
Table 1 compares several vendors' 5-V TTL-compatible bus interface offerings. The comparison is limited to 16 to 20-bit widths because only a few devices having more than 20 bits have been announced. Also, too few functional types are available to make a comparison meaningful at this time. Table 2 describes low-voltage devices.

Device specs and features
The following paragraphs describe the various parameters and features of the products in Table 1 and 2.
Vendor name and brand. All of the vendors listed provide data sheets for their particular brand of broad bus interfaces. Several of the vendors (perhaps all) have alternative source agreements. Designers should check with the particular vendor for current status.
Technology. As shown, a variety of technologies are in use, including bipolar, CMOS, and BiCMOS. Most of the recent broad bus families are BiCMOS.
Width. This article is confined to widths of 16 to 20 bits. In some cases (see vendor's data sheets), there may be individual byte control.
Number of announced devices. Announced devices are not necessarily available in either samples or production. Check with the vendor to determine the exact status and availability of specific device types.
Speed. Speed is the larger of either high-to-low or low-to-high propagation delay through the device. The '240 function (or '245, if there is no '240 in a family) was used as a common benchmark, and the active delay is specified from data input to data output. The other two parameters, enable and disable, refer to time from an input-enable to an active output level from a high-impedance state, and from a disable-input to a high output impedance from an active output, respectively.
Ground bounce. With a large number of outputs that may be simultaneously switching, there can be large and sudden changes in ground path currents. By using many ground pins and by controlling the shape of the switching waveform, the effects of these rapid changes can be largely mitigated. Most vendors routinely include a measure of these effects using a standard test setup. V_OLP , the positive peak voltage on a “quiet output” while all others are undergoing a high-to-low transition, is commonly specified.
Output drive. Dc output drive current capability at the low (sink) and high (source) levels.
Static supply current. Current consumption under nonswitching conditions (for many applications this is the preponderant operating mode). This could be critical for portable equipment design.
I_CC . When an input is at a specified TTL level rather than at 0 V or V_CC , an increase in supply current is caused by a partially turned-on input circuit (a similar condition can occur on a floating input–see “bus hold” below.)
Live insertion/removal. This is the first of several new features to be found in advanced bus interface devices that will be described in detail. Systems that cannot be powered down for repair or modification require interface circuits that will not be damaged or cause damage when they are inserted or removed from a powered connector. One method of accomplishing this is to ensure that the inputs and outputs are high impedances and will withstand sudden large voltage changes. Of the families shown in Table 1, only the Motorola ALExIS family currently has this capability.

Circuit behavior
In a typical BiCMOS Motorola ALExIS circuit (see Fig. 1), the input circuits are high-impedance CMOS with ESD overvoltage protection. The outputs are a combination of bipolar and CMOS and also include ESD protection. A V_CC supply-voltage level-detector senses when the voltage is above or below a specific level; for V_CC = 5 this value is 2.4 V, while for V_CC = 3.3, it is 1.5 V. Above 2.4 V, the device is functional, but will perform to specifications only when V_CC is within its required operating range (5 V+/-10%). Below 2.4 V, the outputs are automatically held in the high-impedance state.
Figure 2 shows the time relationship between output impedance and supply voltage. When power is applied, V_CC increases from zero to its normal operating level over a finite period of time (this time interval depends on many system factors, such as power supply characteristics, capacitive and inductive loading, and connector contact parameters). As V_CC increases and internal circuit thresholds are reached, the outputs latch in the high-impedance state. However, it is only after V_CC passes through the 2.4-V level that the outputs would be allowed to be enabled.
For the outputs to be enabled the first time following power-up, the output-enable (n_OE ) signal must be forced through a negative transition edge (see Fig. 3). Following this edge, and with V_CC held above 2.4 V, further active output enables will occur each time n_OE is enabled low. Conversely, the outputs are held in their high-impedance state when n_OE is high.
When power is removed from the ALExIS device, the sequence is just the opposite. When V_CC exceeds 2.4 V, normal operation occurs. Below 2.4 V, the outputs are locked in the high-impedance state. Thus, whether power is being applied or removed, the inclusion of supply-voltage-sensing circuitry provides for safe operation.

Bus hold
A bus allows for several devices to be wired together. A bus with no activity may be allowed to float (when all device outputs connected to it are in their high-impedance condition). Even though the input/output impedances connected to the bus are high, small amounts of leakage current sourced across the bus can cause bus line voltages to wander, starting at the voltage level that was on the bus prior to three-state (see Fig. 4). This floating voltage may reach the threshold voltage of one or more device inputs resulting in increased supply current or device oscillation.
Designers have tried to circumvent this problem by tying the bus to V_CC through pull-up resistors (RPU) or to ground with pull-down resistors (RPD) as shown in Fig. 5. This technique has several major detriments: it requires extra components, added space, increased cost, and additional power consumption.
The floating-bus problem can be solved with a technique called “bus hold.” To accomplish this, the IC manufacturer includes extra circuitry that holds the bus at the last state prior to three-state, as shown in Table 1. Both Motorola and Texas Instruments include this feature.
The Motorola ALExIS method of bus hold (see Fig. 6) is accomplished quite simply by putting feedback inverter (FBI) around the inverting input circuit, thus latching up the last bus level applied to the input. The amount of hold-current fed back to the input is sufficient to hold the bus inputs away from the threshold region, but is small enough to be easily overridden by bus driver outputs. Thus, without any extra components, the bus is held at its last level before three-state, eliminating floating voltages.

Boundary scan
Boundary scan, or as it is sometimes called, JTAG (Joint Test Action Group), is a result of an industry standard (IEEE 1149.1) for improving system test effectiveness (see Electronic Products, March 1993, p.65). Some of the announced broad bus driver vendors currently include JTAG as an option and others indicate plans to add it. To provide a brief introduction into JTAG's operation, consider the testing of a non-JTAG pc-board assembly (see Fig. 7). If component lead spacing is wide enough, bed-of-nails testing, in which test pins are placed on component lead connections, can be used to test PC board assemblies. However, as lead spacing becomes increasingly dense, it becomes nearly impossible to connect the test nails to the component leads.
The alternative is JTAG circuitry built into the IC. The basic elements of such circuitry are shown in Fig. 8. Inserted between each input and output signal line from the device logic to the package lead is a scan cell. This cell can be portrayed as a flip-flop with two multiplexed inputs, one connected to the appropriate core logic signal and the other to the boundary scan chain (in reality, a scan cell is usually more complex). Additional internal scan-control circuitry, the test access port (TAP) is also included.
To accommodate the internal boundary scan circuits, four additional leads must be made available: TDI (test data input), TDO (test data output), TCK (test clock input), and TMS (test mode select); a fifth lead, TRST (test reset), is optional and not usually included.
Preparing the actual test programs and interpreting the results is a highly structured process, well beyond the purpose of this article. The major intent here is to point out that by incorporating the boundary scan capability, designers can build in testability for isolating chip and board level defects.

Package types
Because of the many leads required for signal, power, ground, and boundary scan, there has been a diversity of packages used for broad bus drivers. All of the vendors offer surface mount packages with lead spacing of either 0.65- or 0.5-mm pitch. The 64-pin fine-pitch quad flatpack (FQFP) with 0.5-mm lead spacing occupies the least board area.

CAPTIONS:

Fig 1. The level detector locks the output in the high-impedance state when V_CC drops below the threshold.

Fig. 2. Control of the output impedance by the V_CC sensor allows safe hot-removal and insertion.

Fig 3. After outputs have been disabled by the V_CC sensor, or on power-up, an active signal, n_OE , must be driven low before outputs will leave high-impedance.

Fig 4. Floating bus voltages could wander past the input threshold when all outputs on the bus are high-impedance.

Fig. 5. Passive external pullup or pulldown resistors solve the float problem but add dissipation.

Fig 6. Active bus-hold, built into some logic families, sources or drains enough current to maintain the bus at its last active level.

FIg 7. Bed-of-nails testers require coarse pin-spacing, increasingly rare

Fig 8. JTAG scan testing requires four extra pins dedicated to test on each package.