Notes on two very interesting new chips this week – FPGAs and data acquisition from Altera and Texas Instruments.
Altera’s new Stratix 10 FPGA family
Altera has introduced their latest FPGA family, Stratix 10. Built using an Intel 14 nm Tri-Gate process, the devices deliver 2x performance, 5.5 million logic elements, heterogeneous 3D system-in package integration, and comprehensive security capabilities. Altera says the new devices have GPU-class floating point computation performance.
The company’s new HyperFlex architecture introduces registers throughout all core interconnect routing segments, enabling register re-timing, pipelining, and other design optimization techniques not practical in conventional FPGA architectures. HyperFlex is said to allow designers to eliminate critical paths and routing delays, and rapidly close timing.
All densities of Stratix 10 will be available with a 64-bit ARM quad-core Cortex-A53 hard processor with a rich feature set of peripherals, including a system memory management unit, external memory controllers, and high-speed communication interfaces.
The devices Secure Design Manager (SDM) delivers sector-based authentication and encryption, multi-factor authentication, and physically un-clonable function (PUF) technology. Altera has partnered with Athena Group and IntrinsicID to deliver encryption acceleration and PUF IP for Stratix 10 FPGAs and SoCs.
Figure 1: Altera Stratix 10 FPGA family
These high-end devices will carry a price premium, many system designs may continue to rely on the 20 nm Arria 10 devices unless integration and performance requirements warrant a shift to the new FPGA. Designers can get started on Stratix 10 designs now using the Fast Forward Compile performance evaluation tools. Engineering samples of Stratix 10 FPGAs and SoCs will be available in the fall of 2015.
Texas Instrument’s high speed data acquisition power house
Is the new 66AK2L06XCMS SoC from TI a DSP chip with data acquisition features, or vice versa? In either case, it will provide some very interesting functionality for those engineers working with sensor data.
The chips Keystone II architecture has four TMS320C66x 1.2 GHz DSP sub-systems for calculating those tough algorithms. It also has two 1.2 GHz Cortex-A15 cores with a 1 Mbyte shared L2 memory. The chip features a digital front-end with digital down/up-conversion functionality and four 7.37 Gbit/s JESD204B serial I/O links for connection to A/D and D/A sub-systems. The IC has a network co-processor, a five-port Ethernet switch, four GbE ports, a security accelerator with support for IPSec, SRTP, and SSL/TLS and up to 6.4 Gbit/s IPSec, a packet accelerator, USB 3.0, and one two lane PCie Gen 2 interface. It has a 72-Bit 1600 MH DDR3 Interface and three enhanced DMA controllers.
Figure 2: The 66AK2L06XCMS SoC from TI.
The IC uses four main hardware elements: Multicore Navigator, TeraNet, and a multicore shared memory controller. Multicore Navigator is an innovative packet-based manager that controls 8K queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based IC uses the 2-Tbit/s capacity of the TeraNet switched central resource to move packets. The multicore shared memory controller enables cores to access shared memory directly without drawing from the TeraNet’s capacity, so packet movement cannot be blocked by memory access.
The DSPs each have fixed-point and floating-point capability with 38.4 GMACS/core and 19.2 Gflops/core and the IC has two FFT coprocessor supporting Up to 1200 Ms/s at FFT size 1024. TeraNet non-blocking switch fabrics enable fast and contention-free internal data movement. The chip has 19 different power domains and uses 11 power supplies. It comes in a 900-pin plastic ball grid array and operates over 0° to 100°C or -40° to 100°C.
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