OL2.JUL–RP
New process expands model availability
A new model development technology offers to expand the availability of
behavioral models for board and system design. Developed by Logic Modeling
Corp. (Beaverton, OR), the technology–called the SmartLogic
process–takes structural device information and uses it to
semiautomatically generate the functions for behavioral models–typically
the most time-consuming part of the model development process. According
to the company, the need for simulation models is exploding as board and
system designers use electronic design automation tools to design the next
generation of multichip modules and fine-line and complex surface-mount
circuit boards. Model availability has become a critical factor in the
adoption of these technologies. Until now, the time required to develop a
behavioral model has depended on both device complexity and the stability
of the chip design. “The temptation has been to start model development
too early–before the chip design was really stable–so that there would
be enough time to write and validate the model,” says Curt Widdoes, chief
technology officer at Logic Modeling. The new process offers a more
efficient method for both the company and the semiconductor vendor. Model
developers have traditionally had to rely on written and oral
communication with the chip design team for model development information.
As a result, the development process has been slowed and the potential for
error increased. The SmartLogic process bypasses this path and uses the
design data already used to develop the chip to create the model, thus
allowing model development to start later and proceed more quickly.
Models developed using the new process require detailed descriptions as
input, typically in VHDL or Verilog structural simulation formats. As this
involves access to proprietary device data, safeguards are included that
protect the semiconductor manufacturer's intellectual property. The
SmartLogic process analyzes the topology of a circuit and applies a
levelization algorithm that orders the execution of the logic primitives
as a single execution stream. The timing information for the function is
added later in a pin-to-pin fashion. Levelization algorithms are applied
to both synchronous and asynchronous logic in standard devices. The
technology is most useful for modeling VLSI devices, in particular those
with architectures composed of reusable logic. It is not suited for memory
arrays, simple logic functions, or programmable devices. Currently, the
process can handle devices of about 100,000-gate equivalents. The first
models developed using the SmartLogic process include the NCR 53C710/720
SCSI controller, Texas Instruments' TMS320C50A digital signal processor,
Motorola's MC68332 microcontroller, and the Cypress VIC068 VMEbus
controller. The models have been validated with the semiconductor vendors'
test information to verify accuracy. Additional models will be released
periodically with updates of Logic Modeling's SmartModel library. For more information, contact Diane Landers of Logic Modeling at 503-531-2252, or .
–Richard Pell Jr.
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