HL11.APR–SGS-Thomson Microelectronics–RM
New Transputer sports 3 million transistors
Communication within- and off-chip improves multiprocessor uses, with
100-Mbit/s serial links
Silicon is here for the radically redesigned T9000 Transputer, packing 3
million transistors including a 16-Kbyte primary cache (see Electronic
Products, June 1991, p. 22). The new chip is not strictly binary
compatible with its predecessors, and its interchip communication links
have changed as well. Like its predecessors, the T9000 is stack oriented.
It has two three-deep stacks, one for the integer unit and one for
floating point. The stacks do not continue in off-chip memory, like a
Forth processor, but rather loads and stores are pushes and pops,
respectively. Since instructions don't identify registers, they are only 1
byte long. The chip includes a 32-bit integer unit, a 64-bit
floating-point unit, a virtual-channel processor, a 16-Kbyte memory, a
programmable 64-bit interface to external memory, and a phase-locked loop
that multiplies the external clock for internal use. All these are
connected by a 4 x 32-bit crossbar for addresses and data. The internal
memory permits four accesses each clock cycle. It can be configured as
cache and/or addressable RAM according to program needs. A hardware
grouper collects as many instructions as the five-stage pipeline can
handle (up to eight) and fires them off at once. The grouper is designed
to recognize common sequences and make them, in effect, into complex
instructions that use as much of the hardware as possible. A group could
thus include two local loads, an ALU operation, and a nonlocal load or
store. The four-way serial links that have characterized all Transputers
are still there in changed form, with four-wire links. A subsidiary chip,
the C101 link adapter, is necessary to connect to earlier Transputers.
The communications capability is boosted by two pieces of hardware. A
hardware packet-switching dispatcher associated with each link
transparently handles up to 64K virtual links. The software need not be
concerned with availability of a link. A new routing chip, the C104,
expands the Transputer connections available and makes any topology
possible. It acts as a nonblocking crossbar between 32 ports. It routes
signals by addresses put into headers by the packet assembler. Latency is
under a microsecond for a single pass. The net effect is that processes
can send messages to each other in a program, and the programmer never
needs to know how many actual Transputers will execute the code. Another
ancillary chip, the C101, connects a T9000 link, either from a T9000 or a
C104, with outside peripheral devices. A third, C100, connects a T9000
link to a first-generation Transputer link. An on-chip scheduler enables
any number of processes to be created and run, with high or low priority.
Context switching takes less than a microsecond. The scheduler may
eliminate the need for a real-time software kernel for many applications.
Control links allow an external host, or another Transputer in a
multiprocessing system, to boot the Transputer without a local boot ROM.
The links also allow access to memory and configuration registers for
debugging. Four I/O pins, called event pins, can be used as hardware
interrupts, or as control lines to external devices. Their response time
is under a microsecond. An external 5-MHz crystal or clock distribution
net feeds the on-chip phase-locked loop, which generates the internal
clocks, currently 50 MHz. A minimum operable system would be one T9000, a
byte-wide boot ROM, a 5-MHz crystal, and a 1-microfarad capacitor.
Development tools include C, C++, and occam compilers as well as a
windowed debugging environment. These are available for Sun or
DOS-Windows. The compilers are designed to optimize code for the grouper.
Bootstrap code, either for ROM or control link, is supplied by the
company. (T9000 Transputer, $450 ea/1,000–samples now.) SGS-Thomson
Microelectronics, Inc. Phoenix, AZ Robert Schmitz 214-466-7403
3130
CAPTION:
The 3-million-transistor T9000 has 16 Kbytes of memory on chip and a
hardware scheduler that takes the place of a real-time kernel.
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