Nonvolatile FPGAs feature 50% cut in price/function

Nonvolatile FPGAs feature 50% cut in price/function

90-nm chips provide instant-on operation and enhanced design security

Featuring a 90-nm process, the LatticeXP2 nonvolatile FPGA family provides up to 40K lookup tables, with 25% speed improvement, dedicated DSP blocks added, and price per function reduced by up to 50%. Static power consumption has been reduced by 30%, using a 1.2-V core voltage.

The 325-MHz devices provide the instant-on operation, enhanced design security, and live update capabilities inherent in the flash FPGA process. At powerup, data in the chips’ flash memory are transferred into SRAM cells for configuration of the device, with device logic available in approximately 1 ms.

Five family members provide 5K to 40K four-input LUTs with embedded block memory of up to 885 Kbits in 18-Kbit dual-port blocks. Up to 12 DSP blocks provide hardwired pipelined multiply and accumulate functions and up to four PLLs allow designers to align and synthesize clocks. Flexible I/O buffers support LVCMOS, SSTL, HSTL, and LVDS I/O standards and interface to 400-MHz DDR2 memory. The family is available in chip-scale ball grid array (csBGA) as well as ftBGA, fpBGA, TQFP, and PQFP packages. (From $12 ea/100,000, 17K LUT LatticeXP2-17—samplesavailable now.)

Lattice Semiconductor , Hillsboro , OR
Brian Kiernan 503-268-8739

http://www.latticesemi.com