NV memory IP comes in 65-nm process

Enabling SoC manufacturers to embed nonvolatile memory at advanced logic processes, the AEON NVM IP uses TSMC’s 65-nm low power process. The IP provides full read and program operation at –40° to 125°C, with minimum 10-year data retention at 125°C.

The IP comes in sizes from 8 bits to 8 Kbits, supports 100,000 write-erase cycles, and is a fully electrically testable NVM block. (From $150,000 — available now.)

Virage Logic , Fremont , CA
Sales 510-360-8000

http://www.viragelogic.com