Open-Silicon, a system-optimized ASIC solution provider and founding member company of the Interlaken Alliance, announced its eighth-generation Interlaken IP core, supporting up to 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC). This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable, making it ideal for highbandwidth networking applications, such as routers, switches, Framer/MAC, OTN switch, packet processors, traffic managers, look aside processors/memories, data center applications, and several other high-end networking and data processing applications.
Open Silicon’s 8th generation Interlaken IP core features:
-Support for maximum bandwidth of 1.2 Tbps
-Support for up to 56 Gbps SerDes data rates
-Increased flexibility by allowing a single instance of the core to have multipl configurations (e.g. a single 1.2 Tbps interface or four 300 Gbps interfaces) selected at power-up
-Multiple user-data interface options 128 bit or 256 bit wide with one, two, four or eight segments
-SerDes width support for 8, 10, 16, 20, 32, 64 and 80-bits
Since 2007 Open-Silicon’s Interlaken IP has been deployed in several different tier-1 networking and computing customer products. Many of these products are shipping in production today in the latest technology nodes in multiple foundries. The unique flexibility and configurability built into Open-Silicon’s Interlaken core meets not only today’s technological requirements, but remains fully compatible with older designs.
“The 3rd-party IP ecosystem has always played a key role in the industry. And now, with the nstoppable growth of high-bandwidth networking applications together with the desire to urther technological advancements on a much quicker cadence, the demand for industry onsortium standards that ensure interoperability grows sharply,” stated Michael Howard, senior research director and advisor, carrier networks at IHS Markit. “It is for these reasons that solutions such as this chip-to-chip Interlaken IP core, will likely have high adoption into nextgeneration routers and switches, packet processors, and high-end networking and data processing applications.”
“The demand for performance and bandwidth for applications in networking is growing xponentially,” said Vasan Karighattam, Vice President of Engineering for Open-Silicon. “With early a decade of experience building the Interlaken core, Open-Silicon has continued to provide its customers with leading-edge custom silicon and IP solutions that power nextgeneration networking products. Open-Silicon remains committed to the Interlaken protocol and providing the highest-performance, most scalable Interlaken IP.”
Open-Silicon’s 8th generation Interlaken IP is available today. For more information, please visit www.open-silicon.com/open-silicon-ips/interlaken-controller-ip/
Open-Silicon will be delivering a Tech Talk titled, “Interlaken – High Speed Chip-to-Chip nterface IP Supporting 1.2 Tbps Bandwidth and up to 56 Gbps SerDes” at Design & Reuse IPSoC 017 in Bangalore, India on Wednesday, April 5. Visit Open-Silicon’s exhibit at the event o learn more about the new Interlaken IP core and other innovative IP and ASIC solutions.
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