Package offers SoC timing signoff solution

The Tempus Timing Signoff Solution for SoC design is said to yield up to an order of magnitude faster performance than traditional timing analysis solutions. The tools uses a massively distributed parallel timing engine which can scale to hundreds of CPUs.

The software also has a path-based analysis engine that leverages multi-core processing to reduce pessimism. With its performance advantage, the Tempus  Timing Signoff Solution enables broader use of path-based analysis than other solutions. It provides multi-mode, multi-corner (MMMC) analysis and physically-aware timing closure and can handle designs containing hundreds of millions of cell instances without compromising accuracy. Available Q3.