Pairing high-bandwidth THA and high-data-rate ADC

Pairing high-bandwidth THA and high-data-rate ADC

Extending high speed converter performance using a high-bandwidth track-and-hold amplifier (THA)

BY ANDREW GLASCOTT-JONES and NICOLAS CHANTIER, e2V
www.e2v.com
AND ROBERT SCHWANKE, Inphi
www.inphi.com

The input bandwidth of an analog-to-digital converter sets its ability to be able to digitize high-frequency input signals. While the analog bandwidth of existing high-speed ADCs is relatively high (for example, EV10AS150 has an analog bandwidth of 5 GHz), accurately sampling signals which are greater than 5 GHz becomes difficult.

Most ADCs use an internal track-and-hold amplifier, which freezes the input signal at a given sample point allowing a more stable signal to be input to the conversion elements. However the internal track-and-hold is not optimized for higher frequencies.

Many different applications use these very high frequencies in the microwave (1 to 30-GHz) realm. Microwave communications is used in cordless phones (1 to 3 GHz), wireless LAN (5 to 6 GHz) and satellite communications (7 to 12 GHz).

Radar applications generally use the 1 to 18-GHz range and include commercial and military airspace phased array radars used to identify and track airplanes, Doppler radars used to track severe weather storms and radar techniques used in electronic warfare.

A new generation of test equipment has expanded on the testing of high-speed signals using digital sampling oscilloscope techniques with high-sample-rate ADCs that can measure data eye diagrams of Gigabit-per-second signals with spectral content from 100 kHz to 30+ GHz. Many of the 10+ Gbits/s signals come out of the various optical communications networks. The ability to provide a digital conversion of these signals in any of these applications without the need for intervening analog components, such as mixers or down-converters, would give advantages in terms of greater flexibility, lower power dissipation, reduced component count and lower overall system cost. The addition of an external track-and-hold amplifier (THA) provides a solution for these applications.

Figure 1 illustrates the principle of the external track-and-hold amplifier circuit. The high-frequency input signal is sampled using a high-performance THA. The signal at the output of the THA is held steady (nearly zero slew rate) for most of the sample period at the input to the ADC. Hence the ADC will be able to more accurately sample this data since it will be less affected by jitter on its sample point.

Fig. 1: Principle of operation and measurement setup.

For example, Inphi produces track-and-hold amplifiers based on indium phoshide (InP) technology, they offer bandwidths up to 18GHz with input voltage ranges of 1 Vp-p. The 1321TH is a dual track-and-hold amplifier with an input bandwidth of 13 GHz. The 1821TH is also a dual track-and-hold amplifier, but with a bandwidth of 18 GHz. Both devices have an aperture jitter of less than 50 fs and integrated output noise of 1.31 mVrms.

As an example, e2v produces high-speed data converters with sample rates of up to 5 Gsamples/s and with bandwidths of up to 5 GHz. The test system outlined here uses as a reference the EV8AQ160 8-bit, 5-Gsample/s ADC.

The combination of these two components can produce a system capable of sampling ultra-high-frequency signals at very high sample rates, one step beyond conventional track-and-hold applications that sample high-speed repetitive signals using time-delay triggering.

The great advantage of using a high-data-rate converter is the increased range of usable bandwidth. The Nyquist sampling theory splits the frequency response of a sampled system into zones, called Nyquist zones. The width of a zone is equal to the sample rate Fs/2.

Unless the system is appropriately filtered, signals in any of the Nyquist zones will be aliased into any of the other zones. The wider the Nyquist zone, the more information can be passed by that system and thus a higher Fs will mean the best possible data transfer. Figure 2 illustrates this; it is evident that wider Nyquist zones mean greater channel capacity.

Fig. 2: Nyquist zones and data channels.

Demonstration unit

The setup for the demonstration unit used evaluation systems for the 1321TH dual track-and-hold amplifier and the EV8AQ160 Quad ADC. The 1321TH evaluation board contains the components along with the appropriate SMA connectors to supply the clocks, input and output signals. The component requires two clocks since it contains two track-and-hold amplifiers used in a master–slave configuration. The clocking arrangement used a single clock with an inverted version to clock the second track-and-hold.

The evaluation system for the EV8AQ160 uses an FMC card containing the ADC and peripheral components; This connects to an FPGA board (Xilinx ML605) using the FMC connectors.PC based acquisition and control software is supplied with the system to control the conversion and display the results.

The measurement connected the differential output of the track-and-hold to the differential input of the EV8AQ160 (channel D on the evaluation board) using dc blocking capacitors. The demo kit has an internal clock, but for the purposes of this measurement an external clock was used.

The EV8AQ160 was programmed to be used at a sample rate of 2.5 Gsamples/s. Although the maximum specified by Inphi is 2 Gsamples/s, measurements at 2.5 Gsamples/s were seen to produce good results.

The maximum signal level of the EV8AQ160 is 500 mV p_p so to avoid overloading the ADC a 3 dB attenuator was placed between the T/H and the ADC on each signal line.

Results

The attenuation of the system at 1 GHz is reduced due to the extra attenuation added to the system to avoid any overloading of the ADC (see Fig. 3 ). Beyond 1 GHz, the detected signal when using just the ADC shows a large attenuation. The track-and-hold amplifier allows the system to be able to detect signals up to 6 GHz with very low attenuation (a 4-dB loss over this frequency range)

Fig. 3: Results.

The effect of the track/hold on the ENOB value is also shown. It can be seen that in the designed bandwidth of the ADC, the track-and-hold slightly degrades the performance of the system however as the frequency is increased the performance of the ADC decreases rapidly as expected. Whereas using the track-and-hold allows the system performance to be maintained.

The SFDR performance up to 6 GHz using the track-and-hold is relatively flat with a value of around -50 dBFS. This is due to reducing slew rate distortion products within the front end of the ADC.

The use of a track-and-hold amplifier in a system with a high-data-rate ADC brings large improvements in the total system performance at frequencies beyond the normal bandwidth of the ADC. This is due to the higher-performance track-and-hold bandwidth and its intrinsic low jitter sampling.

The pairing of a high-bandwidth track-and-hold amplifier and a high-data-rate ADC gives the possibility of sampling GHz signals with usable bandwidths of greater than 1 GHz.

This performance will find many applications in the fields of passive optical networks and direct down-conversion applications in radar and electronic warfare. Other direct down conversion applications, where the track-and-hold can be used instead of a mixer include equalisation of power amplifiers, equalisation of high-speed fiber-optic transmitters.

The EV8AQ160 has two channels able to operate at a sample rate of 2.5 Gsamples/s. It is therefore conceivable that an interleaved system comprising two track-and-hold amplifiers and an EV8AQ160 could offer sample rates of 5 Gsamples/s and hence usable bandwidths of 2.5 GHz. ■