PHY IP targets 28-Gbit/s communication links

The SBMULTC2T28HPM28G PHY IP supports Common Electrical Interface (CEI) standards for 25 and 28 Gbits/s for deployment in high-data-rate chip-to-chip and chip-to-module communication links. The IP can be programmed to support multiple standards.

The IP has an AFE with transmit and receive path circuitry along with auxiliary blocks for clock generation, test, and biasing. The Tx driver is highly programmable with registers to allow adjustment of Tx amplitude, de-emphasis, and pre-emphasis. The Rx architecture includes a multistage continuous time linear equalizer, a passive linear equalizer, and a variable gain amplifier. All stages feature digital offset calibration and adaptive equalization to handle a range of channel conditions.