PLL family produces 3-ps phase jitter

Ideal for FibreChannel and Serial ATA applications, the NB3N3001/3011 PLL family uses an inexpensive reference crystal to generate a differential LVPECL output clock at 106.25 or 212.5 MHz and 100 or 106.25 MHz, respectively.

Housed in TSSOP-8 packages, they provide a typical rms phase jitter of less than 0.3 ps and a noise floor of 135 dBc/Hz at 100-kHz offset. ($1.50 ea/2,500available now.)

ON Semiconductor , Phoenix , AZ
Sales 602-244-6600
http://www.onsemi.com