PMIC algorithms save power at all loads

A variable gate drive algorithm adjusts the gate drive voltage to minimize gate drive losses at low operating loads, and optimize conduction losses at high loads. It is configured to optimize efficiency from the lowest idle state to the highest operating state of high performance server, graphics and desktop solutions. The digital power algorithm increases efficiency up to 15% especially at low loads. It targets voltage regulator solutions for CPU, GPU, and DDR applications.

When applied to server class products, the algorithm can save up to 85-W/server card at peak operation, and 40 W during typical operation. In idle state, the discontinuous-mode operation requires no sensing circuitry and can be configured digitally to optimize performance. In low current modes, the automatic dynamic phase control optimizes the number of operation phases to minimize power losses. The true-digital algorithms can be applied to readily available off-the-shelf components, and do not rely on specific semiconductor products. (Contact 978-640-0011 for pricing and availability.)

CHiL Semiconductor , Tewksbury , MA
Information 978-640-0011
http://www.chilsemi.com