Power-efficient communication engines in FPGAs

Power-efficient communication engines in FPGAs

FPGA cost and power consumption can be reduced using hard standard cell logic gates

BY RAJESH TRIVEDI, Brand Manager
Lattice Semiconductor
www.latticesemi.com

The rapid pace of innovation across industries is driving new approaches to electronic system design. Designers are increasingly seeking to build their next-generation electronic products on flexible platforms that can be customized quickly to create additional, derivative products to meet diverse customer needs.

In addition, in a networked world, electronic equipment of all types must continuously communicate with each other. These two trends are encouraging system engineers to look for flexible design platforms with industry-standard communication interfaces. End-customers as well want low-cost, low-power design platforms that can be manufactured in volume and are competitive in the marketplace.

Efficient communication engines

Field-programmable gate arrays offer a flexible design platform with a variety of resources – high-speed configurable interfaces, embedded memory, digital signal processing and a programmable logic fabric. The cost and power consumption of FPGA platforms can be reduced by selecting widely used functional blocks, which do not vary from application to application, for implementation in hard standard-cell logic gates. FPGAs that provide a balance between a soft programmable fabric and hard, but configurable functional blocks are ideal design platforms for system manufacturers.

One set of functional blocks that is an ideal candidate for hard implementation in FPGAs are communication interfaces. An increasing variety of electronic equipment use industry-standard communication interfaces such as PCI Express, Gigabit Ethernet, Tri-speed Ethernet, and Serial RapidIO. An ideal solution will implement OSI Layer-2 (Link Layer) functionality for each protocol and additional OSI Layer-1 physical layer functionality in hard logic as efficient communication engines.

Fig. 1: The LatticeECP4 FPGA has 4 to 16 SERDES organized in quads of four each and up to 22 hard-wired communication engines.

The primary benefit of using hardwired communication engines is a dramatic reduction in power consumption. An average two-input NAND gate consumes power in nanowatts, whereas a four-input lookup table (LUT4) in FPGAs consumes power in hundreds of nanowatts. But the FPGA LUT4 performs the function of at least 10 standard cell gates — and therefore a standard cell gate implementation yields a net power reduction of a factor of 10.

The hardwired implementation of popular communication protocols also reduces the required semiconductor die area by a factor of 30, which leads to lower cost. The logic fabric in typical midrange FPGAs runs at speeds up to 250 MHz. The hard implementation of communication protocols allows the same FPGAs to process data at speeds up to 600 MHz. Thus, the hardwired communication engines enable low-cost midrange FPGAs to process high-speed data.

FPGA implementation

An example FPGA family with available hard-coded logic is the recently announced LatticeECP4 FPGA family, with up to four 6 Gbit/s SERDES (see Fig. 1 ). Each communication engine offers up to a tenfold power and cost reduction over similar FPGA implementations. The 6-Gbit/s SERDES channels take less than 175 mW each. They are designed and characterized to meet the rigorous data and control plane timing requirements of each protocol.

The configurable communication engines can be customized by embedding proprietary code in the surrounding FPGA logic fabric. The complete solution also includes an easy-to-use software tool to connect the communication engine with the surrounding logic fabric and with high-speed serial interfaces. Designers can also access network control and statistics vectors within the engines.

An FPGA-based design platform with efficient communication engines allows design engineers to build sophisticated networking equipment with lower power and lower cost. And, though the communication engines are hardwired, they can be configured using the soft logic in the FPGA fabric. This approach permits designers to enjoy the best of both worlds. ■