PRODUCT APPLICATION: Medical electronics

Signal compression solves exploding data bandwidth requirements and cost concerns in ultrasound equipment

BY ALLAN EVANS
Samplify Systems
Santa Clara, CA
http://www.samplify.com

In the quest for ever-higher image quality, ultrasound equipment manufacturers are radically expanding their transducer channel counts, demanding higher-resolution ADCs and higher frame rates from their image processing. These demands not only create bottlenecks within the data acquisition subsystems of ultrasound machines, but also jeopardize manufacturers’ ability to use commodity PC components to control development costs. New signal compression techniques are being developed that directly address these concerns across the range of ultrasound equipment from handheld devices, using PDA form factors, to advanced 3D consoles.

Let’s look at bandwidth and cost issues

In ultrasound machines, piezoelectric transducer elements convert electrical pulses into acoustic pulses and convert the resulting acoustic echoes to analog electrical signals. These transducer elements are arranged into arrays ranging from as few as 16 or 32 transducers for handheld devices, to thousands for 3D machines.

Different transducers are used for different types of scans and each type of transducer uses piezoelectric elements tuned to a particular frequency ranging from 2.5 MHz for an abdominal scan, to 10 MHz for carotid or vascular scans. Individual cable strands carry each analog signal to the data acquisition subsystem where they are sampled by high-speed ADCs clocked anywhere from 40 to 65 Msamples/s.

Regardless of the center frequency of the pulse used for a particular transducer, the ADCs operate at a fixed clock rate because they need to handle all possible transducer types. In a typical configuration of 256 elements for a high-end machine, these ADCs, operating at 50 Msamples/s with 12-bit resolution, generate over 200 Gbits/s of aggregate data that must be processed.

Signal-compression technology can reduce these bottlenecks within the data acquisition subsystem.

The responsibility for processing this data belongs to the ultrasound machine’s beamforming array, which coherently combines data across all ADC channels through a delay and weighting operation. By changing the delay and weights, the beam is steered to scan across the area of interest on successive firings of pulses.

The scan rate is limited by physics, as sound waves travel through the body at a fixed rate, independent of center frequency. Hence, scan rates cannot be increased by simply firing pulses at a faster repetition rate. Instead, ultrasound designers form multiple beams or scan lines simultaneously from the same echo response using synthetic aperture techniques.

This process requires different delay and weights for each beam for each channel. Also, the maximum dispersion between elements can represent thousands of samples, which define the maximum memory depth requirement for all channels. For a system that forms four beams simultaneously, the memory bandwidth requirement can exceed 1 Tbit/s.

When semiconductor mask costs were low, ultrasound manufacturers designed their own proprietary ASICs for this beamforming function. Since these legacy ASICs can no longer meet the channel density and synthetic aperture requirements of current generation machines, and mask costs on 90- or 65-nm processes are prohibitive for even market leading OEMs, ultrasound designers are turning to FPGAs for their beamforming functionality.

As they complete these FPGA-based beamformers, ultrasound designers begin to realize that memory for the sample delays dominate FPGA resources. In essence, they have turned FPGAs into very expensive memory chips. Because the FPGA-based SRAM consumes static power, the delay memory also becomes the top-power consumer.

In addition to delay memory consuming power, I/O between the ADCs and the FPGA-based beamformer are a significant power consumer as well. Each high-speed ADC channel connects to the beamformer array via a high-speed serial LVDS interface.

At up to 30 mW per LVDS interface, the power consumed by 64 such links amounts to nearly 2 W. By comparison, Intel’s new Atom processor is targeted to consume around 1 W for ultraportable products. Clearly a disproportionate amount of power is being consumed by I/O instead of the CPU, which is doing the heavy lifting in the application.

Standard PC hardware generates the ultrasound images from the beamformed outputs of the data acquisition subsystem. Therefore, the interfaces of choice are PCIe and SATA for storage. As the number of channels and simultaneous beams increase, the throughput requirements across these interfaces increase quadratically. For example, a portable system forming four beams, with 16-bit resolution at the 50-Msample/s rate, generates 3.2 Gbits/s of data, which exceeds the throughput of a single lane of PCIe as well as SATA 3.0, which are available in notebook motherboard chipsets. In advanced 3D systems, where 16 beams or more may be formed and the resolution can be as high as 24 bits, the data rates can approach 20 Gbits/s, which exceed even eight-lane PCIe.

Raw data

Storage of raw data also is becoming a requirement to give sonographers VCR-style control functionality over images. These functions, called cineloop, give the sonographer the ability to advance or reverse frame by frame and to regenerate the image with different windowing settings.

However, to enable these features, raw data must be stored in memory or on disk. For the same portable application generating 3.2 Gbits/s of data, a 5-min scan can generate 120 Gbytes of data, which can consume all of the capacity of portable-form-factor hard-disk drives, requiring frequent docking of the machine.

Signal-compression technology

Signal-compression technology can reduce these bottlenecks within the data acquisition subsystem. For optimum results when applying signal-compression techniques, algorithms must be amenable to hardware implementation, in both FPGA and silicon forms, and software implementation on Intel processors, graphics processors, and cell processors. Because ultrasound manufacturers are concerned about signal quality, the algorithm must support a lossless mode, particularly for initial adoption by the market.

If the compression algorithm can be controlled to maintain signal quality metrics such as SNR, then near lossless modes can be employed. Any compression noise introduced by a near lossless mode must be spectrally white to avoid introduction of any artifacts into the finished images.A good example is the Prism algorithm from Samplify. It is a low-complexity algorithm amenable to real-time hardware implementation in FPGA or ASIC. It is also available for Intel processors and can be ported to GPUs and cell processors. Prism’s lossless mode delivers nearly 3:1 compression on raw ultrasound echoes from the ADC.

At this compression level, the power consumed by I/O between the ADC and the beamformer can be reduced by two thirds, making it less than that of the Intel Atom CPU in a portable application. Delay memory is also reduced within the beamformer FPGA. This reduction can enable a doubling of the channel density within the FPGA, reducing the power per channel by half.

This compression algorithm maintains a user-specified dynamic range setting to deliver 4:1 compression on the beamformer output with only a degradation of 1 dB in dynamic range. In this near lossless mode, the compression noise is spectrally flat so as not to introduce artifacts into the finished image. ■

For more on signal compression, visit http://www2.electronicproducts.com/AnalogMixICs.aspx.