While the number of cores on a central processing unit (CPU) are often synonymous with processing capacity, one cannot simply increase the number of processing units and call it a day. Scalable coherence and on-chip interconnections are crucial for creating a stable product; our inability to produce a more robust communication bus is part of the reason why the majority of contemporary CPUs have remained capped at four to eight cores for years. One MIT professor has finally devised a solution that’s said to push the boundaries up to 36 cores.
Earlier this year at the International Symposium on Computer Architecture, Li-Shiuan Peh, the Singapore Professor of Electrical Engineering and Computer Science at MIT, has unveiled a 36-core chip that uses a “network-on-chip” style bus to resolve the communication bottleneck that normally plagues CPUs as the number of cores increases. Described as having “little internets,” each core in the chip has an associated router that transmits bundles of data “packets” down one of many different paths, depending on the network’s overall condition. Theoretically, this system resolves the issue of only two cores being granted exclusive access to the bus at a time.
By contrast, the network-on-a-chip cores are connected only to those immediately adjacent to them, allowing them to great multiple paths to the destination that avoids those that are already congested. This allows the CPU to maintain cache coherence as every core has its own memory cache.
After ironing some kinks associated with data snooping — requests sent by other cores for data — Peh and his colleagues will load their prototype CPU with a version of Linux, tailored to run on 36 cores, and evaluate the performance of real applications.
Source: MIT
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