Rambus Introduces Memory Controller Interface Solution for Industry-standard DDR3 DRAM

Rambus Introduces Memory Controller Interface Solution for Industry-standard DDR3 DRAM

Rambus Inc. has announced the introduction of its memory controller interface solution for industry-standard DDR3 DRAM. The fully integrated hard macro cell provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600 MHz.

Complete, drop-in DDR3 PHY architecture enables data rates of up to 1600 MHz

Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, workstations, and network communications. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or application-specific integrated circuit (ASIC) chip.